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參數(shù)資料
| 型號(hào)： | VSC6424 |
| 廠商： | VITESSE SEMICONDUCTOR CORP |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 500 Mb/s Video Shift Register IC |
| 中文描述： | 10-BIT, DSP-VIDEO SHIFT REGISTER, PQFP128 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, HEAT SINK, PLASTIC, QFP-128 |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 364K |
| 代理商： | VSC6424 |
VITESSE
Preliminary Datasheet
VSC6424
500 Mb/s Video
Shift Register IC
Page 6
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
G52236-0, Rev 3.0
7/13/99
HBLANK
or
VBLANK
must be driven low for at least one clock cycle two clock cycles before the desired
point of blanking. See Figure 6 for a timing illustration of this function.
Retimer
The chip also contains a retimer function. This function works in
DEMUX
mode. The
RETIME
signal is
routed to
DOUT<7>
through a flip-flop. The flip-flop is internally clocked by the low speed ECL output clock
(
CLKE
). This function is depicted in the detailed block diagram (Figure 3) below. See Figure 5 for a timing
illustration.
Figure 2: Multiplexer Detailed Block Diagram
Termination
It is recommended to leave all unused ECL outputs floating. It is recommended that unused ECL inputs be
terminated low (-2V supply). Refer to the following table recommended input termination for all levels.
Table 4: Input Termination Recommendations
Type
State
Input
ECL
ECL
TTL
TTL
High
Low
High
Low
ground via a diode
-2V supply
+3.3V supply
Ground
A<0:4>
HBLANK
VBLANK
DOUT<0:6>
8
8
AEN/RETIME
OEN
MODE
7
Retimer
DOUT<7>
40
MUX
CLKOUT
S<0:2>
OPS
CLK
High
Speed
Interface
(ECL)
Output
Latch
CLKE
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