參數(shù)資料
型號(hào): VSC7121
廠商: Vitesse Semiconductor Corporation.
英文描述: Quad Port Bypass Circuit for 1.0625 Gbit/sec Fibre Channel Arbitrated Loop Disk Arrays
中文描述: 四端口旁路電路1.0625 Gbit / sec光纖通道仲裁環(huán)路磁盤陣列
文件頁數(shù): 8/12頁
文件大?。?/td> 77K
代理商: VSC7121
VITESSE
Data Sheet
VSC7121
Quad Port Bypass Circuit for 1.0625 Gbit/sec
Fibre Channel Arbitrated Loop Disk Arrays
Page 8
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
8/31/98
G52110-0, Rev. 4.1
Package Pin Description
Table 4: Pin Description
Pin #
Name
Description
9, 10
IN-, IN+
INPUT - Differential (Biased at VDD/2). Differential inputs from the downstream PBC
port.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 1.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 2.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 3.
INPUT - Differential (Biased at VDD/2). Serial input from the local transmitter on PBC
port 4.
INPUT - TTL. A LOW selects the “BYPASS” mode causing the output of the previous
port to propagate to next port or OUT. When HIGH, this signal selects “NORMAL”
mode which routes the previous port to the local output, L_SOn, and routes the local
input, L_SIn, to the next port or OUT .
OUTPUT - Differential (Biased at VDD-1.32V).
Serial output driving the local receiver corresponding to PBC port 1.
OUTPUT - Differential (Biased at VDD-1.32V)
Serial output driving the local receiver corresponding to PBC port 2.
OUTPUT - Differential (Biased at VDD-1.32V)
Serial output driving the local receiver corresponding to PBC port 3.
OUTPUT - Differential (Biased at VDD-1.32V)
Serial output driving the local receiver corresponding to PBC port 4.
OUTPUT - Differential (Biased at VDD - 1.32V) Serial output driving the upstream PBC
port.
3, 4
L_SI1-, L_SI1+
40, 41
L_SI2-, L_SI2+
34, 35
L_SI3-, L_SI3+
27, 28
L_SI4-, L_SI4+
15-18
SEL1, SEL2,
SEL3, SEL4
6, 7
L_SO1-,
L_SO1+
L_SO2-,
L_SO2+
L_SO3-,
L_SO3+
L_SO4-,
L_SO4+
43, 44
37, 38
30, 31
25, 24
OUT-, OUT+
2, 14, 20-21,
32
5, 26, 29 36,
42
1, 8, 11-13,
19, 22-23,
33, 39
VDD
Digital Logic Power Supply. 3.3V Supply for digital logic.
VDDP
High-Speed Output Power Supply. 3.3V Supply for PECL drivers.
VSS
Ground. Ground pins are physically attached to the die mounting surface, and are an
important part of the thermal path. For best thermal performance, all ground pins should
be connected to a ground plane, using multiple vias if possible.
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