參數(shù)資料
型號(hào): VSC7123QU
廠商: VITESSE SEMICONDUCTOR CORP
元件分類: 網(wǎng)絡(luò)接口
英文描述: Development kit; Kit Contents:Evaluation Board; For Use With:CS4955A; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No RoHS Compliant: No
中文描述: DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝: 10 X 10 MM, THERMALLY ENHANCED, PLASTIC, QFP-64
文件頁(yè)數(shù): 7/18頁(yè)
文件大小: 208K
代理商: VSC7123QU
V
ELOCITY
TM
VITESSE
VSC7123
10-Bit Transceiver for Fibre
Channel and Gigabit Ethernet
Data Sheet
G52212-0, Rev 4.3
03/25//01
Page 7
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Figure 5: Receive Timing Waveforms
Table 3: Receive AC Characteristics
NOTE: (1) Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3.
Parameters
Description
Min.
Max.
Units
Conditions
T
1
TTL Outputs Valid prior to
RCLK/RCLKN rise
TTL Outputs Valid after
RCLK or RCLKN rise
Delay between rising edge of
RCLK to rising edge of
RCLKN
Period of RCLK and
RCLKN
R(0:9), COMDET, SIGDET,
RCLK and RCLKN rise and
fall time
4.0
3.0
3.0
2.0
ns
At 1.0625Gb/s
At 1.25Gb/s
At 1.0625Gb/s
At 1.25Gb/s
T
2
ns
T
3
10 x T
RX
-500
10 x T
RX
+500
ps
T
RX
is the bit period of the
incoming data on Rx.
T
4
1.98 x
T
REFCLK
2.02 x
T
REFCLK
ps
Whether or not locked to
serial data.
T
R
, T
F
2.4
ns
Between V
IL(MAX)
and
V
IH(MIN)
, into 10pf load.
R
LAT
Latency from RX to R(0:9)
12 bc + 1 ns
13 bc + 9 ns
bc
ns
bc = bit clock
ns = nano second
8B/10B IDLE pattern.
bc = bit clocks
T
LOCK(1)
Data acquisition lock time
1400
bc
RCLK
R(0:9)
RCLKN
T
2
T
3
Data Valid
Data Valid
T
1
T
4
Data Valid
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