參數(shù)資料
型號(hào): VSC8021
廠商: Vitesse Semiconductor Corporation.
英文描述: 2.5Gb/s SONET-Compatible 8-Bit MUX/DEMUX Chipset
中文描述: 容量高達(dá)2.5GB / s的SONET的兼容8位/解復(fù)用器芯片組
文件頁(yè)數(shù): 2/17頁(yè)
文件大小: 220K
代理商: VSC8021
VITESSE
Data Sheet
VSC8021/VSC8022
2.5Gb/s SONET-Compatible
8-Bit MUX/DEMUX Chipset
Page 2
G52028-0, Rev 4.1
05/25/01
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
An internal Phase Detector and Phase Adjust Circuit are used to facilitate the two asynchronous circuits to
work with each other. The Phase Detector and the Phase Adjust Circuit work together to adjust the internal
clock CLK8 to make sure the set up and hold conditions are met for the internal registers. CLK8 is derived from
CLKI and the RCLK is a non-phase varying byte clock output. The edge sensitive SYNC signal is simply the
control signal that enables the Phase Detector circuitry.
As a summary, the CLKI is the high-speed clock input. The BYCLK is the external byte clock. The CLK8
is the internal byte clock derived from CLKI, phase-adjusted if SYNC is enabled. The RCLK is a non-phase-
adjusted divided-by-8 clock generated from CLKI. The phase of RCLK, RCLKN is not affected by the self-
adjusting circuitry, therefore it can be used as a system reference clock. RCLK, RCLKN can be used by the sys-
tem designer to generate BYCLK, BYCLKN. The self-positioning timer and RCLK, RCLKN allow for the cre-
ation of very tight parallel data timing for the VSC8021.
Figure 1: VSC8021 Block Diagram
ERR
Phase Adjustable
Byte Clock Output
CLK8
CLK8N
Serial Data Output
8:1
Multiplexer
Timing
Generator
DO
DON
High Speed
Clock Inputs
CLKI
CLKIN
Byte Clock
Inputs
BYCLK
BYCLKN
High Speed
Clock
CO
CON
Independent
Byte Clock Output
RCLK
RCLKN
8
8
Parallel
Data
D1
D1N
D8
D8N
Phase
Adjust
SYNC
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