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參數(shù)資料
| 型號： | VT8501 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | APOLLO MVP4 |
| 中文描述： | 阿波羅MVP4 |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 243K |
| 代理商： | VT8501 |
VT8501 Apollo MVP4
Revision 1.3
February 1, 2000
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3-
Features
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High-Performance DRAM Controller
64-bit DRAM interface synchronous with host CPU (66//100 MHz) or internal Memory Clock (100 MHz)
Concurrent CPU and AGP access
Supports both standard PC100 and
“
Virtual Channel
”
PC100 SDRAMs as well as FPG and EDO DRAMs
Different DRAM types (FPG, EDO, and SDRAM) may be used in mixed combinations
Different DRAM timing for each bank
Dynamic Clock Enable (CKE) control for SDRAM power reduction
Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs
6 banks up to 768MB DRAMs
Flexible row and column addresses
64-bit data width only
3.3V DRAM interface
Programmable I/O drive capability for MA, command, and MD signals
Optional bank-by-bank ECC (single-bit error correction and multi-bit error detection) or EC (error checking only)
for DRAM integrity
Two-bank interleaving for 16Mbit SDRAM support
Two-bank and four bank interleaving for 64Mbit SDRAM support
Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU
Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while
accessing the current bank)
Four cache lines (16 quadwords) of CPU/cache to DRAM write buffers
Four quadwords of CPU/cache to DRAM read prefetch buffers
Concurrent DRAM writeback
Read around write capability for non-stalled CPU read
Burst read and write operation
5-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM
6-1-1-1-2-1-1-1 back-to-back accesses for SDRAM
BIOS shadow at 16KB increment
Decoupled and burst DRAM refresh with staggered RAS timing
Programmable refresh rate and refresh on populated banks only
CAS before RAS or self refresh
Sophisticated Power Management Features
Independent clock stop controls for CPU / SDRAM, Internal AGP and PCI bus
PCI and AGP bus clock run and clock generator control
Suspend power plane preserves memory data
Suspend-to-DRAM and Self-Refresh operation
Dynamic clock gating for internal functional blocks for power reduction during normal operation
Low-leakage I/O pads
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相關(guān)代理商/技術(shù)參數(shù) |
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| VT8601 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Slot-1 / Socket-370 PCI North Bridge With Integrated AGP 2D / 3D Graphics Accelerator and Advanced Memory Controller |
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| VT8N1 | 制造商:PERKINELMER 制造商全稱:PerkinElmer Optoelectronics 功能描述:Photoconductive Cells and Analog Optoisolators (Vactrols) |
| VT8N2 | 制造商:PERKINELMER 制造商全稱:PerkinElmer Optoelectronics 功能描述:Photoconductive Cells and Analog Optoisolators (Vactrols) |
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