參數(shù)資料
型號(hào)： W110
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 383K
代理商： W110
I
W110 Dual-Speed Ethernet Controller
I
–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
8
Oki Semiconductor
MII Signals
The MII interface signals are listed below. Signal direction is with respect to the W110 function block. See
IEEE 802.3u standard documentation for further information.
Signal
Type
Assertion
Description
TX_CLK
Input
—
Transmit Symbol Clock. This transmit nibble or symbol clock input is derived from
the PHY layer. The following table indicates the frequency and type of Transmit
Symbol Clock for various PHY options.
TXCEN
Output
HIGH
Transmit Clock Enable. In 10-Mbps mode, TXCEN is the 10-MHz ENDEC clock
divided by four. In 100-Mbps mode, the W110 asserts TXCEN HIGH.
TXD[3:0]
Output
—
Transmit Nibble Data. This bus outputs data from the transmit function,
synchronous with TX_CLK
TX_EN
Output
HIGH
Transmit Enable. The transmit function outputs this enable signal, synchronous
with TX_CLK.
TX_ER
Output
HIGH
Transmit Error. When asserted HIGH, this signal indicates a transmission error.
This is a synchronous signal with the rising edge of TX_CLK.
CRS
Input
HIGH
Carrier Sense. This input receives information via the MII multiplex and is
considered to be asynchronous.
COL
Input
HIGH
Collision. This input transmits information via the MII multiplex and is considered
to be asynchronous. For half-duplex transceivers, the assertion of this signal
indicates simultaneous transmission and reception. Full-duplex transceivers
never activate this signal.
RX_CLK
Input
—
Receive Symbol Clock. The PHY layer produces this symbol clock or receive
nibble input. The following table indicates the frequency and type of Receive
Symbol Clock for various PHY options.
RXCEN
Output
HIGH
Receive Clock Enable. In 10-Mbps mode, RXCEN is the 10-MHz ENDEC clock
divided by four. In 100-Mbps mode, the W110 assert SRXCEN HIGH.
RXD[3:0]
Input
—
Receive Nibble Data. This synchronous input indicates that nibble data has been
received on the rising edge of RX_CLK.
RX_DV
Input
HIGH
Receive Data Valid. This synchronous input validates received data on the rising
edge of RX_CLK.
RX_ER
Input
HIGH
Receive Error. The W110 reads this signal input on the rising edge of RX_CLK. The
presence of receive errors usually indicates bad wiring.
Mode
TX_CLK
25 MHz
2.5 MHz
10 MHz
TXCEN
HIGH
HIGH
100-Mbps MII PHY
10-Mbps MII PHY
10-Mbps ENDEC
2.5 MHz (
1
/
4
duty cycle)
Mode
MRXC
25 MHz
2.5 MHz
10 MHz
RXCEN
HIGH
HIGH
100-Mbps MII PHY
10-Mbps MII PHY
10-Mbps ENDEC
2.5 MHz (
1
/
4
duty cycle)
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