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參數(shù)資料
| 型號： | W134MHT |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK DIFF DIRECT RAMBUS 24QSOP |
| 標(biāo)準包裝： | 1,000 |
| 系列： | Direct Rambus™ |
| 類型： | * |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 400MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | * |
| 封裝/外殼： | * |
| 供應(yīng)商設(shè)備封裝： | * |
| 包裝： | * |
W134
........................ Document #: 38-07426 Rev. *C Page 8 of 11
Notes:
1. Represents stress ratings only, and functional operation at the maximums is not guaranteed.
2. Gives the nominal values of the external components and their maximum acceptable tolerance, assuming ZCH = 28.
3. Do not populate CF. Leave pads for future use.
4. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
5. Refclk jitter measured at VDDIR (nom)/2.
6. If input modulation is used: input modulation is allowed but not required.
7. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and VAC < 100 mV.
8. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew
generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
Absolute Maximum Conditions[1]
Parameter
Description
Min.
Max.
Unit
VDD, ABS
Max. voltage on VDD with respect to ground
–0.5
4.0
V
VI, ABS
Max. voltage on any pin with respect ground
–0.5
VDD + 0.5
V
External Component Values[2]
Parameter
Description
Min.
Max.
Unit
RS
Serial Resistor
39
±5%
RP
Parallel Resistor
51
±5%
CF
Edge Rate Filter Capacitor
4–15[3]
±10%
pF
CMID
AC Ground Capacitor
470 pF
0.1
F±20%
Operating Conditions[4]
Parameter
Description
Min.
Max.
Unit
VDD
Supply Voltage
3.135
3.465
V
TA
Ambient Operating Temperature
0
70
°C
tCYCLE,IN
Refclk Input Cycle Time
10
40
ns
tJ,IN
Input Cycle-to-Cycle Jitter[5]
–
250
ps
DCIN
Input Duty Cycle over 10,000 Cycles
40
60
%tCYCLE
FMIN
Input Frequency of Modulation
30
33
kHz
PMIN
[6]
Modulation Index for Triangular Modulation
–
0.6
%
Modulation Index for Non-Triangular Modulation
–
0.5[8]
%
tCYCLE,PD
Phase Detector Input Cycle Time at PclkM & SynclkN
30
100
ns
tERR,INIT
Initial Phase error at Phase Detector Inputs
–0.5
0.5
tCYCLE,PD
DCIN,PD
Phase Detector Input Duty Cycle over 10,000 Cycles
25
75
tCYCLE,PD
tI,SR
Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,
SynclkN, and Refclk
14
V/ns
CIN,PD
Input Capacitance at PclkM, SynclkN, and Refclk[7]
–7
pF
DCIN,PD
Input Capacitance matching at PclkM and SynclkN[7]
–0.5
pF
CIN,CMOS
Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and
Refclk)[7]
–10
pF
VIL
Input (CMOS) Signal Low Voltage
–
0.3
VDD
VIH
Input (CMOS) Signal High Voltage
0.7
–
VDD
VIL,R
Refclk input Low Voltage
–
0.3
VDDIR
VIH,R
Refclk input High Voltage
0.7
–
VDDIR
VIL,PD
Input Signal Low Voltage for PD Inputs and StopB
–
0.3
VDDIPD
VIH,PD
Input Signal High Voltage for PD Inputs and StopB
0.7
–
VDDIPD
VDDIR
Input Supply Reference for Refclk
1.235
3.465
V
VDDIPD
Input Supply Reference for PD Inputs
1.235
2.625
V
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