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參數(shù)資料
| 型號： | W24010S-70LI |
| 英文描述： | x8 SRAM |
| 中文描述： | x8的SRAM |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 216K |
| 代理商： | W24010S-70LI |
W24010
- 4 -
AC Characteristics, continued
(V
DD
= 5 V
±
10%; V
DD
= 3 V
±
10%; V
SS
= 0 V; T
A
(
°
C) =-20 to 85 for LE, -40 to 85 for LI)
Read Cycle
PARAMETER
SYM.
5 V
3 V
UNIT
MIN.
MAX.
MIN.
MAX.
Read Cycle Time
T
RC
70
-
100
-
nS
Address Access Time
T
AA
-
70
-
100
nS
Chip Select Access Time
T
ACS
-
70
-
100
nS
Output Enable to Output Valid
T
AOE
-
35
-
50
nS
Chip Selection to Output in Low Z
T
CLZ
*
10
-
15
-
nS
Output Enable to Output in Low Z
T
OLZ
*
5
-
5
-
nS
Chip Deselection to Output in High Z
T
CHZ
*
-
30
-
35
nS
Output Disable to Output in High Z
T
OHZ
*
-
30
-
35
nS
Output Hold from Address Change
T
OH
10
-
15
-
nS
These parameters are sampled but not 100% tested
Write Cycle
PARAMETER
SYM.
5 V
3 V
UNIT
MIN.
MAX.
MIN.
MAX.
Write Cycle Time
T
WC
70
-
100
-
nS
Chip Selection to End of Write
T
CW
50
-
70
-
nS
Address Valid to End of Write
T
AW
50
-
70
-
nS
Address Setup Time
T
AS
0
-
0
-
nS
Write Pulse Width
T
WP
50
-
70
-
nS
Write Recovery Time
CS1
, CS2, WE
T
WR
0
-
0
-
nS
Data Valid to End of Write
T
DW
30
-
50
-
nS
Data Hold from End of Write
T
DH
0
-
0
-
nS
Write to Output in High Z
T
WHZ
*
-
25
-
30
nS
Output Disable to Output in High Z
T
OHZ
*
-
25
-
30
nS
Output Active from End of Write
T
OW
5
-
10
-
nS
These parameters are sampled but not 100% tested
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W24010S-70SL | x8 SRAM |
| W24010T-70LE | x8 SRAM |
| W24010 | 128K×8bit CMOS Static RAM(128K×8位CMOS靜態(tài)RAM) |
| W2409GT1 | DC to DC Converter |
| W2409HD1 | DC to DC Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W24010S-70SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| W24010T-70LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| W24010T-70LI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| W24010T-70SL | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
| W24010U-70LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 SRAM |
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