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參數(shù)資料
| 型號(hào)： | W332M72V-100SBC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 SYNCHRONOUS DRAM, 7 ns, PBGA208 |
| 封裝： | 16 X 22 MM, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 257K |
| 代理商： | W332M72V-100SBC |
5
White Electronic Designs
W332M72V-XBX
March 2006
Rev. 3
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
TABLE 1 – BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
2
A0
0
0-1
1
1-0
4
A1
A0
0
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
8
A2
A1
A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
Page
(y)
n = A 0-9
(location 0-y)
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
Not Supported
FIGURE 3 – MODE REGISTER DEFINITION
NOTES:
1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-9 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-9 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-9 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-9 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-9 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
A11
Reserved*
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = 0, 0
to ensure compatibility
with future devices.
A12
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| W332M72V-100SBM | 32M X 72 SYNCHRONOUS DRAM, 7 ns, PBGA208 |
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| W332M72V-100SBI | 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 100MHZ, 208 PBGA, INDUSTRIAL TEMP. - Bulk |
| W332M72V-100SBM | 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 100MHZ, 208 PBGA, MIL-TEMP. - Bulk |
| W332M72V-125BC | 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 125MHZ, 219 PBGA, COMMERCIAL TEMP. - Bulk |
| W332M72V-125BI | 制造商:White Electronic Designs 功能描述:DRAM Module SDRAM 256Mbyte 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 125MHZ, 219 PBGA, INDUSTRIAL TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W332M72V-125BM | 制造商:Microsemi Corporation 功能描述:32M X 72 SDRAM, 3.3V, 125MHZ, 219 PBGA, MIL-TEMP. - Bulk |
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