
W33D0001 SERIES
Publication Release Date: July 1999
- 7 -
Revision A3
1.1 The Function Control Bits, continued
BIT
FUNCTION
252
Normal mode data reset control bit.
(This bit will cause the 128 dots' data reset to "0").
0: Non-reset the 128 dots' data. (Default value)
1: Resets the 128 dots' data to "0". (It is a level active signal)
253
RDATA pin output status control bit
0: RDATA pin with high impedance.
1: RDATA pin work as output pin in the read mode but H-Z in write mode.
254
Timer bit. (This bit can disable or enable the Timer mode)
0: Timer mode can be shown on the LCD panel. (Default value)
1: Timer mode cannot be shown on the LCD panel.
255
Clock bit. (This bit can disable or enable the Clock mode)
0: Clock mode can be shown on the LCD panel. (Default value)
1: Clock mode cannot be shown on the LCD panel.
1.2 The transceiver function controlled by a
P:
The W33D0001 can display the data on the LCD panel. These data are inputted by a serial
transmission function from an external device such as a microprocessor. In normal mode and clock
mode, the data can be read or written by a
P with a transceiver function at the rising edge of RCLK
or WCLK pin. The RCLK pin and WCLK pin must normally be set to a high state if there is no data
reception and transmission.
1.2.1 Switch Read or Write Function
If the W33D0001 is in write function mode, the first falling edge of RCLK will switch the write function
to read function and the
P can read data from the RCLK pin and RDATA pin, and vice versa. Refer
to Figure 2. When the write function is reactivated (function changed from read to write or power on
reset), the first 8 bits sent by the
P sends through the WCLK pin and WDATA pin indicate the
starting address of the desired read or write data. Refer to Figure 3 and Figure 4.
1.2.2 Serial Data Written by
P
A
P can send serial data and clock to the W33D0001 through the WDATA pin and WCLK pin,
respectively. When the
P writes data to the W33D0001 in normal mode or clock mode, the P first
does a dummy read before sending a serial starting address to the W33D0001 through the WDATA
pin and WCLK pin.
The serial starting address includes 8 bits which, from the first bit to the 8th bit, represent the LSB to
the MSB of the starting address, respectively. Lastly, the
P sends the serial data to the W33D0001
through the WDATA and WCLK pins. The serial data address stored in the W33D0001 is increased
by one when the WCLK pin receives one clock form
P. Refer to Figure 3.