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參數(shù)資料
| 型號： | W3E16M72SR-200BC |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM, 0.75 ns, PBGA219 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-219 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 671K |
| 代理商： | W3E16M72SR-200BC |
10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3E16M72SR-XBX
February 2005
Rev. 2
REGISTER ELECTRICAL CHARACTERISTICS
Parameter
Test Conditions
VCC and VCCQ Min
Typ
Max
Unit
II
All inputs
VI = VCC or GND
2.7V
-5
+5
μA
ICC
Static standby
RESET# = GND
2.7V
10
μA
Static operating
RESET# = VCC, VI = VIH(AC) or VIL(AC)
IO = 0
112
mA
ICCD
Dynamic operating
– clock only
RESET# = VCC, VI = VIH(AC) or VIL(AC), CK and CK# switching
50% duty cycle
IO = 0
2.5V
56
μA/ MHz
Dynamic operating
– per each data input
RESET# = VCC, VI = VIH(AC) or VIL(AC). CK and CK#
switching 50% duty cycle. All data input switching at one-half
clock frequency, 50% duty cycle
180
μA/clock
MHz
Note: All typical values are at VCC = 2.5V, TA = 25°C.
NOTE: Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions greater than those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
SELF REFRESH*
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH and
is automatically enabled upon exiting SELF REFRESH (200
clock cycles must then occur before a READ command
can be issued). Input signals except CKE are “Don’t Care”
during SELF REFRESH.
The procedure for exiting self refresh requires a sequence
of commands. First, CK must be stable prior to CKE going
back HIGH. Once CKE is HIGH, the DDR SDRAM must
have NOP commands issued for tXSNR, because time
is required for the completion of any internal refresh in
progress.
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for 200 clock cycles before
applying any other command.
* Self refresh available in commercial and industrial temperatures only.
REGISTER RECOMMENDED OPERATING CONDITIONS
Parameter/Condition
Min
Max
Unit
VIH AC high-level input voltage
Data inputs VREF+310mV
V
VIL AC low-level input voltage
Data inputs
VREF-310mV
V
VIH High-level input voltage
RESET#
1.7
V
VIL Low-level input voltage
RESET#
0.7
V
Note: The RESET# input of the device must be held at a valid logic level (not oating) to ensure proper
device operation.
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on VCC, VCCQ Supply relative to Vss
-1 to 3.6
V
Voltage on I/O pins relative to VSS
-1 to 3.6
V
Operating Temperature TA (Mil)
-55 to +125
°C
Operating Temperature TA (Ind)
-40 to +85
°C
Storage Temperature, Plastic
-55 to +125
°C
CAPACITANCE (NOTE 13)
Parameter
Symbol
Max
Unit
Input Capacitance: CK/CK#
CI1
8
pF
Addresses, BA0-1 Input Capacitance
CA
10
pF
Input Capacitance: All other input-only pins
CI2
9
pF
Input/Output Capacitance: I/Os
CIO
10
pF
BGA THERMAL RESISTANCE
Description
Symbol
Max
Units Notes
Junction to Ambient (No Airow)
Theta JA
14.2
°C/W
1
Junction to Ball
Theta JB
10.8
°C/W
1
Junction to Case (Top)
Theta JC
4.1
°C/W
1
Note 1: Refer to AN #0001 at www.whiteedc.com in the application notes
section for modeling conditions.
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