參數(shù)資料
型號(hào)： W3E232M16S-266STIG
廠(chǎng)商： WHITE ELECTRONIC DESIGNS CORP
元件分類(lèi)： DRAM
英文描述： 64M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁(yè)數(shù)： 5/22頁(yè)
文件大?。?/td> 0K
代理商： W3E232M16S-266STIG
W3E232M16S-XSTX
13
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2005
Rev. 1
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY*
IDD SPECIFICATIONS AND CONDITIONS
-40°C ≤ TA +85°C; VccQ = +2.6 ±0.1V, Vcc = +2.6V ±0.1V Notes: 1-5, 10, 12, 14, 46
Parameter/Condition
Symbol
Max
Units
Notes
DDR333
DDR266
DDR200
OPERATING CURRENT: One bank; Active-Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
IDD0
260
230
mA
22, 47,
53
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1
320
290
mA
22, 47,
53
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down
mode; tCK=tCK (MIN); CKE = (LOW)
IDD2P
10
mA
23, 32,
49
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock
cycle. VIN = VREF for DQ, DQS, and DM
IDD2F
90
85
mA
50, 54
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK=tCK (MIN); CKE = (LOW)
IDD3P
70
60
mA
23, 32,
49, 54
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK
(MIN); IOUT = 0mA
IDD3N
100
90
mA
22, 54
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK
(MIN); IOUT = 0mA
IDD4R
330
290
mA
22, 47,
53
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK
(MIN) DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
350
310
270
mA
22, 53
AUTO REFRESH BURST CURRENT:
tREFC = tRFC(MIN)
IDD5
580
560
mA
49, 54
tREFC = 7.8us
IDD5A
20
mA
27, 47,
54
SELF REFRESH CURRENT; CKE ≤0.2V
Standard
IDD6
10
mA
11, 54
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed:
tCK=tCK (MIN); Address and control inputs change only during Active READ, or
WRITE commands
IDD7
810
800
700
mA
22, 48,
53
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W3E232M16S-400STC 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM
W3E232M16S-400STCG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM
W3E232M16S-400STI 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM
W3E232M16S-400STIG 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM
W3E232M16S-XSTX 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:2x32Mx16bit DDR SDRAM
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