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參數(shù)資料
| 型號(hào)： | W3EG2128M72AFSR335AD3S |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 272K |
| 代理商： | W3EG2128M72AFSR335AD3S |
W3EG2128M72AFSR-D3
-AD3
5
White Electronic Designs
January 2006
Rev. 3
FINAL
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
ICC SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Parameter
Symbol
Rank 1
Conditions
DDR400@CL=3
Max
DDR333@CL=2.5
Max
DDR266@CL=2,
2.5
Max
Units
Rank 2
Standby
State
Operating Current
ICC0
One device bank; Active - Precharge; tRC = tRC (MIN);
tCK = tCK (MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
3870
2780
2790
mA
ICC3N
Operating Current
ICC1
One device bank; Active-Read-Precharge Burst = 2;
tRC = tRC (MIN); tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per clock cycle.
4410
3780
mA
ICC3N
Precharge Power-
Down Standby
Current
ICC2P
All device banks idle; Power-down mode; tCK = tCK
(MIN); CKE = (low)
180
rnA
ICC2P
Idle Standby
Current
ICC2F
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address and other
control inputs changing once per clock cycle. VIN =
VREF for DQ, DQS and DM.
1980
1620
mA
ICC2F
Active Power-Down
Standby Current
ICC3P
One device bank active; Power-Down mode; tCK
(MIN); CKE = (low)
1620
1260
mA
ICC3P
Active Standby
Current
ICC3N
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
2160
1800
mA
ICC3N
Operating Current
ICC4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); lOUT = 0mA.
4500
3870
mA
ICC3N
Operating Current
ICC4W
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
4590
4050
3690
rnA
ICC3N
Auto Refresh
Current
ICC5
tRC = tRC (MIN)
7290
6120
mA
ICC3N
Self Refresh
Current
ICC6
CKE
≤ 0.2V
180
mA
ICC6
Operating Current
ICC 7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address
and control inputs change only during Active Read or
Write commands.
9180
8190
8100
mA
ICC3N
Note:
These parameters serve to support both SAMSUNG and MICRON components based modules.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG2128M72AFSR335AD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA |
| W3EG2128M72AFSR403AD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA |
| W3EG2128M72AFSR-AD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA |
| W3EG2128M72AFSR-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL, FBGA |
| W3EG2256M72ASSR202AJD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:4GB - 2x256Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
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