參數(shù)資料
型號(hào)： W3EG64128S265D3M
廠商： MICROSEMI CORP-PMG MICROELECTRONICS
元件分類(lèi)： DRAM
英文描述： 128M X 64 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁(yè)數(shù)： 10/12頁(yè)
文件大?。?/td> 294K
代理商： W3EG64128S265D3M
White Electronic Designs
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
December 2006
Rev. 6
W3EG64128S-D3
-JD3
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 299: VCC = VCCQ = +2.5V ± 0.2V
AC Characteristics
403
335
262/263/265
202
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Units
Notes
Access window of DQs from CK, CK#
tAC
-0.70
+0.70
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
16
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
16
Clock cycle time
CL=3
tCK (3)
5
7.5
6
13
7.5
13
7.5
13
ns
22
CL=2.5 tCK (2.5)
6
13
6
13
7.5
13
7.5
13
ns
22
CL=2
tCK (2)
7.5
13
7.5
13
7.5
13
10
13
ns
22
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
14,17
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
14,17
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
17
Access window of DQS from CK, CK#
tDQSCK
-0.60
+0.60
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group,
per access
tDQSQ
0.40
0.45
0.5
ns
13,14
Write command to rst DQS latching transition
tDQSS
0.72
1.28
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH, tCL
ns
18
Data-out high-impedance window from CK, CK#
tHZ
+0.70
+0.75
ns
8,19
Data-out low-impedance window from CK, CK#
tLZ
-0.70
-0.75
ns
8,20
Address and control input hold time (fast slew rate)
tIHf
0.60
0.75
0.90
ns
6
Address and control input set-up time (fast slew rate)
tISf
0.60
0.75
0.90
ns
6
Address and control input hold time (slow slew rate)
tIHs
0.60
0.80
1
ns
6
Address and control input setup time (slow slew rate)
tISs
0.60
0.80
1
ns
6
Address and control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
12
15
ns
DQ-DQS hold, DQS to rst DQ to go non-valid, per
access
tQH
tHP-tQHS
ns
13,14
Data hold skew factor
tQHS
0.55
0.75
ns
ACTIVE to PRECHARGE command
tRAS
40
70,000
42
70,000
40
120,000
45
120,000
ns
15
ACTIVE to READ with Auto precharge command
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
55
60
65
ns
AUTO REFRESH command period
tRFC
70
72
75
ns
21
相關(guān)PDF資料
PDF描述
W3EG64128S403JD3S 128M X 64 DDR DRAM MODULE, 0.7 ns, DMA184
W7NCF02GH30IS7CG 128M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF128H20CS5BG 8M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF128H20CSABG 8M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
W7NCF128H20IS9EG 8M X 16 FLASH 3.3V PROM CARD, 150 ns, UUC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3EG64128S265JD3 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
W3EG64128S335AD4 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL
W3EG64128S335BD4 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL
W3EG64128S335D3 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
W3EG64128S335JD3 制造商:WEDC 制造商全稱(chēng):White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*