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參數(shù)資料
| 型號(hào)： | W3EG64128S403JD3S |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.7 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 294K |
| 代理商： | W3EG64128S403JD3S |
White Electronic Designs
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
December 2006
Rev. 6
W3EG64128S-D3
-JD3
ADVANCED
IDD SPECIFICATIONS AND TEST CONDITIONS
VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V
Includes DDR SDRAM component only
Parameter
Symbol Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5
Max
DDR266@
CL=2
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge; tRC=tRC (MIN);
tCK=tCK (MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
2200
1840
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per clock cycle.
2520
2080
mA
Precharge Power-
Down Standby Current
IDD2P All device banks idle; Power-down mode; tCK=tCK
(MIN); CKE=(low)
80
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle; tCK=tCK (MIN); CKE
= high; Address and other control inputs changing
once per clock cycle. VIN = VREF for DQ, DQS and
DM.
880
720
mA
Active Power-Down
Standby Current
IDD3P One device bank active; Power-Down mode; tCK
(MIN); CKE=(low)
720
560
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM
and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
960
800
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
2640
2120
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
2680
2360
2080
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
3720
3120
mA
Self Refresh Current
IDD6
CKE 0.2V
96
80
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4) with auto
precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address
and control inputs change only during Active Read or
Write commands.
4800
4040
4000
mA
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| W3EG64128S-AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S-BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL |
| W3EG64128S-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG64128S-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG64129S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1G- 128Mx64 DDR SDRAM UNBUFFERED |
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