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參數(shù)資料
| 型號： | W3EG6418S265JD3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 代理商： | W3EG6418S265JD3 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG6418S-D3
-JD3
May 2005
Rev. 3
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
Operating
Current
IDD0
One device bank; Active - Precharge; tRC=tRC (MIN);
tCK=tCK (MIN); DQ,DM and DQS inputs changing once
per clock cycle; Address and control inputs changing
once every two cycles.
1000
880
mA
Operating
Current
IDD1
One device bank; Active-Read-Precharge Burst = 2;
tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and
control inputs changing once per clock cycle.
1080
960
mA
Precharge
Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down mode; tCK=tCK (MIN);
CKE=(low)
24
mA
Idle Standby
Current
IDD2F
CS# = High; All device banks idle; tCK=tCK (MIN); CKE =
high; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS and DM.
360
mA
Active Power-
Down Standby
Current
IDD3P
One device bank active; Power-Down mode; tCK (MIN);
CKE=(low)
200
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.
400
mA
Operating
Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; TCK= TCK (MIN); lOUT = 0mA.
1120
1040
mA
Operating
Current
IDD4W
Burst = 2; Writes; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
1120
1000
mA
Auto Refresh
Current
IDD5
tRC = tRC (MIN)
2120
1760
mA
Self Refresh
Current
IDD6
CKE
≤ 0.2V
24
mA
Operating
Current
IDD7A
Four bank interleaving Reads (BL=4) with auto precharge
with tRC=tRC (MIN); tCK=tCK (MIN); Address and control
inputs change only during Active Read or Write
commands.
2840
2640
mA
* Module IDD was calculated on the basis of component IDD and can be different measured according to DQ loading cap.
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| W3EG6418S-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx64 DDR SDRAM UNBUFFERED |
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