- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄203626 > W3EG6462S265JD3 (MICROSEMI CORP-PMG MICROELECTRONICS) 64M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 PDF資料下載
參數(shù)資料
| 型號： | W3EG6462S265JD3 |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 254K |
| 代理商： | W3EG6462S265JD3 |
White Electronic Designs
W3EG6462S-D3
-JD3
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
May 2005
Rev. 4
ADVANCED
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
AC CHARACTERISTICS
403
335
262
263/265
202
PARAMETER
SYMBOL MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX UNITS NOTES
Address and control input setup time (slow slew rate)
tISS
0.6
0.80
1
ns
12
Address and Control input pulse width (for each
input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
2
12151515
ns
DQ-DQS hold, DQS to rst DQ to go non-valid, per
access
tQH
tHP
-
tQHS
tHP
-
tQHS
tHP
-
tQHS
tHP
-
tQHS
tHP
-
tQHS
ns
22, 23
Data hold skew factor
tQHS
0.50
0.55
0.75
ns
ACTIVE to PRECHARGE command
tRAS
40 70,000 42 70,000 40 120,000 40 120,000 40 120,000 ns
31, 48
ACTIVE to READ with Auto precharge command
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRC
55
60
65
ns
AUTO REFRESH command period
tRFC
70
75
ns
43
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
PRECHARGE command period
tRP
15
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
37
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
37
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
00000
ns
18, 19
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
17
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
21111
tCK
Data valid output window
na
tQH - tDQSQ
ns
22
REFRESH to REFRESH command
tREFC
70.3
μs21
Average periodic refresh interval
tREFI
7.8
μs21
Terminating voltage delay to VCC
tVTD
00000
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG6465S202D4C | 64M X 64 DDR DRAM MODULE, DMA200 |
| W3EG6465S262D4C | 64M X 64 DDR DRAM MODULE, DMA200 |
| W3EG7262S202JD3 | DDR DRAM MODULE, DMA184 |
| W3EG7262S265JD3 | DDR DRAM MODULE, DMA184 |
| W3F11A1018AT3A | 1 FUNCTIONS, 100 V, 0.3 A, FEED THROUGH CAPACITOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG6462S335D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S335JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S403D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S403JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6462S-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。