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參數(shù)資料
| 型號： | W3EG6466S335AD4M |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 64 DDR DRAM MODULE, 0.7 ns, DMA200 |
| 封裝： | SO-DIMM-200 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大小： | 210K |
| 代理商： | W3EG6466S335AD4M |
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3EG6466S-AD4
-BD4
January 2005
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specications without notice.
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC
OPERATING CONDITIONS
AC CHARACTERISTICS
335
262
265/202
UNITS NOTES
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
-0.75
+0.75
-0.75
+0.75
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
Clock cycle time
CL = 2.5 tCK (2.5)
6
13
7.5
13
7.5
13
ns
39, 44
CL = 2
tCK (2)
7.5
13
7.5
13
7.5/10
13
ns
39, 44
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.60
+0.60
-0.75
+0.75
-0.75
+0.75
ns
DQS input high pulse width
tDQSH
0.35
tCK
DQS input low pulse width
tDQSL
0.35
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.4
0.5
ns
22, 23
Write command to rst DQS latching transition
tDQSS
0.75
1.25
0.75
1.25
0.75
1.25
tCK
DQS falling edge to CK rising - setup time
tDSS
0.20
tCK
DQS falling edge from CK rising - hold time
tDSH
0.20
tCK
Half clock period
tHP
tCH,tCL
ns
8
Data-out high-impedance window from CK/CK#
tHZ
+0.70
+0.75
ns
16, 36
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.75
ns
16, 36
Address and control input hold time (fast slew rate)
tIHF
0.75
0.90
ns
12
Address and control input setup time (fast slew rate)
tISF
0.75
0.90
.900
ns
12
Address and control input hold time (slow slew rate)
tIHS
0.8
1
ns
12
Address and control input setup time (slow slew rate)
tISS
0.8
1
ns
12
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG6466S335BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6466S-AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6466S-BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL |
| W3EG6467S202D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
| W3EG6467S262D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx64 DDR SDRAM UNBUFFERED |
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