- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68454 > W3EG7217S265D3 (WHITE ELECTRONIC DESIGNS CORP) 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 PDF資料下載
參數(shù)資料
| 型號： | W3EG7217S265D3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 235K |
| 代理商： | W3EG7217S265D3 |
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W3EG7217S-D3
December 2004
Rev. 1
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C TA 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes DDR SDRAM Component Only
Parameter
Symbol
Conditions
DDR266@CL = 2
Max
DDR266@CL = 2.5
Max
DDR200@CL = 2
Max
Units
Operating Current
IDD0
One device bank; Active = Precharge; tRC = tRC(MIN); tCK =
tCK(MIN); DQ,DM and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two
cycles.
900
945
mA
Operating Current
IDD1
One device bank; Active-Read-Precharge; Burst = 2; tRC =
tRC(MIN);tCK = tCK (MIN); Iout = 0mA; Address and control
inputs changing once per clock cycle.
1080
mA
Precharge Power-
Down Standby Current
IDD2P
All device banks idle; Power- down mode; tCK = tCK(MIN);
CKE = (low)
27
mA
dle Standby Current
IDD2F
CS# = High; All device banks idle; tCK = tCK(MIN); CKE =
high; Address and other control inputs changing once per
clock cycle. VIN = VREF for DQ, DQS and DM.
405
360
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down mode; tCK(MIN); CKE
= (low)
225
180
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One device bank; Active-
Precharge; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and
DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle.
450
405
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK = tCK(MIN); IOUT = 0mA.
1170
1125
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One device bank active;
Address and control inputs changing once per clock cycle;
tCK = tCK(MIN); DQ,DM and DQS inputs changing twice per
clock cycle.
1125
1080
mA
Auto Refresh Current
IDD5
tRC = tRC(MIN)
1980
mA
Self Refresh Current
IDD6
CKE
≤ 0.2V
27
18
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL = 4) with auto precharge
with tRC = tRC (MIN); tCK = tCK(MIN); Address and control
inputs change only during Active Read or Write commands.
2970
2925
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG7218S265BD4 | 16M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| W3EG72255S263AJD3SG | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG72255S265JD3MG | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG72255S262JD3S | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| W3EG72255S263AJD3SG | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG7217S-D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM REGISTERED, ECC w/PLL |
| W3EG7218S202AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S202BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S262AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
| W3EG7218S262BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:128MB - 16Mx72 DDR SDRAM UNBUFFERED w/PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復。