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參數(shù)資料
| 型號： | W3EG72255S263JD3 |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 14/14頁 |
| 文件大小： | 237K |
| 代理商： | W3EG72255S263JD3 |
W3EG72255S-D3
-JD3
-AJD3
9
White Electronic Designs
November 2004
Rev. 2
PRELIMINARY
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
335
262/263/265
202
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Units
Notes
ACTIVE to READ or WRITE delay
tRCD
18
20
ns
PRECHARGE command period
tRP
18
20
ns
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
19
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
tCK
DQS write preamble setup time
tWPRES
0
ns
10,11
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
9
Write recovery time
tWR
15
ns
Internal WRITE to READ command delay
tWTR
111
tCK
Data valid output window
NA
tQH-tDQSQ
ns
13
REFRESH to REFRESH command interval
tREFC
70.3
μs
12
Average periodic refresh interval
tREFI
7.8
μs
12
Terminating voltage delay to VCC
tVTD
000
ns
Exit SELF REFRESH to non-READ command
tXSNR
75
80
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
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| W3EG72255S263JD3XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
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