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參數(shù)資料
| 型號： | W3EG7235S-JD3 |
| 英文描述： | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 中文描述： | 256MB的- 2x16Mx72寄存ECC DDR內(nèi)存，瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 318K |
| 代理商： | W3EG7235S-JD3 |
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7235S-JD3
PRELIMINARY
November 2004
Rev. 2
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes PLL and Register Power
Parameter
Operating Current
Rank 1
I
DD0
Conditions
One device bank; Active = Precharge; t
RC
= t
RC
(MIN);
t
CK
= t
CK
(MIN); DQ,DM and DQS inputs changing
once per clock cycle; Address and control inputs
changing once every two cycles.
One device bank; Active-Read-Precharge; Burst = 2;
t
RC
= t
RC
(MIN);t
CK
= t
CK
(MIN); Iout = 0mA; Address
and control inputs changing once per clock cycle.
All device banks idle; Power- down mode; t
CK
=
t
CK
(MIN); CKE = (low)
CS# = High; All device banks idle; t
CK
= t
CK
(MIN);
CKE = high; Address and other control inputs
changing once per clock cycle. V
IN
= V
REF
for DQ,
DQS and DM.
One device bank active; Power-down mode;
t
CK
(MIN); CKE = (low)
CS# = High; CKE = High; One device bank; Active-
Precharge; t
RC
= t
RAS
(MAX); t
CK
= t
CK
(MIN); DQ,
DM and DQS inputs changing twice per clock cycle;
Address and other control inputs changing once per
clock cycle.
Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per
clock cycle; t
CK
= t
CK
(MIN); I
OUT
= 0mA.
Burst = 2; Writes; Continous burst; One device bank
active; Address and control inputs changing once per
clock cycle; t
CK
= t
CK
(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
t
RC
= t
RC
(MIN)
CKE
≤
0.2V
Four bank interleaving Reads (BL = 4) with auto
precharge with t
RC
= t
RC
(MIN); t
CK
= t
CK
(MIN);
Address and control inputs change only during Active
Read or Write commands.
DDR266@CL = 2
Max
2475
DDR266@CL = 2.5
Max
2340
DDR200@CL = 2
Max
2340
Units
mA
Rank2
Stand By
State
I
DD3N
Operating Current
I
DD1
2565
2475
2475
mA
I
DD3N
Precharge Power-
Down Standby Current
dle Standby Current
I
DD2P
54
54
54
mA
I
DD2P
I
DD2F
1120
1030
1030
mA
I
DD2F
Active Power-Down
Standby Current
Active Standby Current
I
DD3P
450
360
360
mA
I
DD3P
I
DD3N
1210
1120
1120
mA
I
DD3N
Operating Current
I
DD4R
2655
2520
2520
mA
I
DD3N
Operating Current
I
DD4W
2610
2475
2475
mA
I
DD3N
Auto Refresh Current
Self Refresh Current
Operating Current
I
DD5
I
DD6
I
DD7A
3500
329
4455
3410
311
4320
3375
346
4320
mA
mA
mA
I
DD3N
I
DD6
I
DD3N
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| W3EG7236S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
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| W3EG7262S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
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