- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361782 > W3EG7235S202JD3 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL PDF資料下載
參數(shù)資料
| 型號： | W3EG7235S202JD3 |
| 英文描述： | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| 中文描述： | 256MB的- 2x16Mx72寄存ECC DDR內(nèi)存，瓦特/鎖相環(huán) |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 318K |
| 代理商： | W3EG7235S202JD3 |
7
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7235S-JD3
PRELIMINARY
November 2004
Rev. 2
I
DD1
: OPERATING CURRENT : ONE BANK
1. Typical Case : V
CC
=2.5V, T=25°C
2. Worst Case : V
CC
=2.7V, T=10°C
3. Only one bank is accessed with t
RC
(min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. I
OUT
= 0mA
4. Timing Patterns :
DDR200 (100 MHz, CL=2) : t
CK=
10ns, CL2,
BL=4, t
RCD=
2*t
CK
, t
RAS=
5*t
CK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
DDR266 (133MHz, CL=2.5) : t
CK=
7.5ns,
CL=2.5, BL=4, t
RCD=
3*t
CK
, t
RC=
9*t
CK
, t
RAS=
5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL=2,
BL=4, t
RCD
=3*t
CK
, t
RC
=9*t
CK
, t
RAS
=5*t
CK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
I
DD7A
: OPERATING CURRENT : FOUR BANKS
1. Typical Case : V
CC
=2.5V, T=25°C
2. Worst Case : V
CC
=2.7V, T=10°C
3. Four banks are being interleaved with t
RC
(min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4. Timing Patterns :
DDR200 (100 MHz, CL=2) : t
CK
=10ns, CL2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=3*t
CK
, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
DDR266 (133MHz, CL=2.5) : t
CK
=7.5ns,
CL=2.5, BL=4, t
RRD
=3*t
CK
, t
RCD
=3*t
CK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DDR266 (133MHz, CL=2) : t
CK
=7.5ns, CL2=2,
BL=4, t
RRD
=2*t
CK
, t
RCD
=2*t
CK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
DETAILED TEST CONDITIONS FOR DDR SDRAM I
DD1
& I
DD7A
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG7235S262JD3 | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7235S265JD3 | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7235S-JD3 | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7236S202D3 | 256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
| W3EG7236S262D3 | 256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG7235S262JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7235S265JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7235S-JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC, w/PLL |
| W3EG7236S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
| W3EG7236S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。