- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361782 > W3EG7236S-D3 256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL PDF資料下載
參數(shù)資料
| 型號(hào)： | W3EG7236S-D3 |
| 英文描述： | 256MB - 32Mx72 DDR SDRAM REGISTERED, w/PLL |
| 中文描述： | 256MB的- 32Mx72 DDR SDRAM的注冊(cè)，瓦特/鎖相環(huán) |
| 文件頁(yè)數(shù)： | 6/12頁(yè) |
| 文件大?。?/td> | 185K |
| 代理商： | W3EG7236S-D3 |
6
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W3EG7236S-D3
PRELIMINARY
November 2004
Rev. 1
I
DD
SPECIFICATIONS AND TEST CONDITIONS
0°C
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Includes PLL and register power
Parameter
Operating Current
Symbol
I
DD0
Conditions
One device bank; Active - Precharge;
t
=t
(MIN); t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
One device bank; Active-Read-
Precharge Burst = 2; t
=t
(MIN);
t
=t
(MIN); l
= 0mA; Address
and control inputs changing once per
clock cycle.
All device banks idle; Power-down
mode; t
CK
=t
CK
(MIN); CKE=(low)
DDR266@CL=2
Max
DDR266@CL=2.5
Max
DDR200@CL=2
Max
Units
1120
1030
985
mA
Operating Current
I
DD1
1390
1300
1210
mA
Precharge Power-
Down Standby
Current
Idle Standby Current
I
DD2P
27
27
27
rnA
I
DD2F
CS# = High; All device banks idle;
t
=t
(MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. V
IN
= V
REF
for
DQ, DQS and DM.
One device bank active; Power-Down
mode; t
CK
(MIN); CKE=(low)
CS# = High; CKE = High; One device
bank; Active-Precharge; t
=t
(MAX); t
=t
(MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; T
CK
= T
CK
(MIN); l
OUT
= 0mA.
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; t
=t
(MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
t
RC
= t
RC
(MIN)
535
490
472
mA
Active Power-Down
Standby Current
Active Standby
Current
I
DD3P
315
270
225
mA
I
DD3N
805
715
670
mA
Operating Current
I
DD4R
1840
1570
1390
mA
Operating Current
I
DD4W
1840
1570
1345
rnA
Auto Refresh
Current
Self Refresh Current
Operating Current
I
DD5
1930
1795
1660
mA
I
DD6
I
DD7A
CKE
≤
0.2V
Four bank interleaving Reads (BL=4)
with auto precharge with t
=t
(MIN); t
=t
(MIN); Address and
control inputs change only during
Active Read or Write commands.
337
337
337
mA
3536
2831
2426
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3EG7262S202D3 | 512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S202JD3 | 512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S262D3 | 512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S262JD3 | 512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S265D3 | 512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3EG7262S202D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S262D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S262JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7262S265D3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2X32Mx72 DDR SDRAM UNBUFFERED |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。