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參數(shù)資料
| 型號： | W3EG7264S202BD4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 197K |
| 代理商： | W3EG7264S202BD4SG |
W3EG7264S-AD4
-BD4
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
January 2005
Rev. 3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Parameter
Symbol Conditions
DDR333@CL=2.5 DDR266@CL=2, 2.5
DDR200@CL=2
Units
Max
Operating Current
IDD0
One device bank; Active - Precharge;
(MIN); DQ,DM and DQS inputs
changing once per clock cycle; Address
and control inputs changing once every
two cycles. TRC=TRC(MIN); TCK=TCK
2205
2025
mA
Operating Current
IDD1
One device bank; Active-
Read-Precharge; Burst = 2;
TRC=TRC(MIN);TCK=TCK (MIN); Iout
= 0mA; Address and control inputs
changing once per clock cycle.
2610
2340
mA
Precharge Power-Down
Standby Current
IDD2P
All device banks idle; Power-down
mode; TCK=TCK(MIN); CKE=(low)
72
mA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
TCK=TCK(MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
900
810
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-down
mode; TCK(MIN); CKE=(low)
540
450
mA
Active Standby Current
IDD3N
CS# = High; CKE = High; One
device bank; Active-Precharge;
TRC=TRAS(MAX); TCK=TCK(MIN); DQ,
DM and DQS inputs changing twice per
clock cycle; Address and other control
inputs changing once per clock cycle.
1080
900
mA
Operating Current
IDD4R
Burst = 2; Reads; Continous burst; One
device bank active;Address andcontrol
inputs changing once per clock cycle;
TCK=TCK(MIN); IOUT = 0mA.
2655
2250
mA
Operating Current
IDD4W
Burst = 2; Writes; Continous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
TCK=TCK(MIN); DQ,DM and DQS inputs
changing twice per clock cycle.
2655
2250
mA
Auto Refresh Current
IDD5
TRC=TRC(MIN)
3375
3015
mA
Self Refresh Current
IDD6
CKE ≤ 0.2V
72
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with TRC=TRC (MIN);
TCK=TCK(MIN); Address and control
inputs change only during Active Read
or Write commands
4770
4050
mA
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| W3EG7264S202JD3 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR SDRAM UNBUFFERED |
| W3EG7264S262AD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL |
| W3EG7264S262BD4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 2x32Mx72 DDR ECC SDRAM UNBUFFERED w/PLL |
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