- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄68457 > W3H128M72ER2-400SBI (MICROSEMI CORP-PMG MICROELECTRONICS) 128M X 72 DDR DRAM, 0.6 ns, PBGA255 PDF資料下載
參數(shù)資料
| 型號： | W3H128M72ER2-400SBI |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 72 DDR DRAM, 0.6 ns, PBGA255 |
| 封裝： | 23 X 21 MM, 1.27 MM PITCH, PLASTIC, BGA-255 |
| 文件頁數(shù)： | 16/34頁 |
| 文件大?。?/td> | 1028K |
| 代理商： | W3H128M72ER2-400SBI |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
W3H128M72ER-XNBX
23
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
February 2009
Rev. 6
PRELIMINARY
White Electronic Designs Corp. reserves the right to change products or specications without notice.
Symbol
Parameter
Test Conditions
VCC
MIN
TYP1
MAX
UNIT
IL
All inputs
VI = VCC or GND
1.9 V
±5
μA
ICC
Static standby
RESET# = GND
IO = 0
100
μA
Static operating RESET# = VCC, VI = VIH(AC) or VIL(AC)
1.9 V
40
mA
ICCD
Dynamic
operating clock
RESET# = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK# switching 50% duty
cycle
IO = 0
1.8 V
28
μA/
MHz
Dynamic
operating per
each data input
RESET# = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK# switching 50% duty
cycle, one data input switching at one-
half clock frequency, 50% duty cycle
18
μA/
clock
MHz/D
input
ICCDLP
Chip-select-
enabled
low-power active
mode - clock
only
RESET# = VCC, VI = VIH(AC) or VIL(AC)
CLK and CLK# switching 50% duty
cycle
IO = 0
1.8 V
27
μA/
MHz
Chip-select-
enabled
low-power active
mode
RESET# = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK# switching 50% duty
cycle, one data input switching at one-
half cock frequency, 50% duty cycle
2
μA/
clock
MHz/D
input
1
All typical calues are at VCC = 1.8 v, TA = 25C.
Symbol
Parameter
Test Conditions
MIN
MAX
UNIT
fclock
Clock frequency
500
MHz
tw
Pulse duration, CLK, CLK# high or low
1
ns
tact
Differential inputs active time (see note 2)
10
ns
tinact
Differential inputs inactive time (see note 3)
15
ns
tsu
Set up time
DCS# before CLK↑, CLK#↓, CSR#
high,CSR# before CLK↑, CLK↓, DCS#
high
0.7
ns
DCS# before CLK↑,CLK#↓, CSR# low
0.5
DODT, DCKE, and Data before CLK↑,
CLK#↓
0.5
th
Hold time
DCS#, DODT, DCKE, and Data after
CLK↑, CLK#↓
0.5
ns
NOTE 1. All input slew rates are 1 V/ns ±20%
2. VREF must be held at a valid input level and data inputs must be held low for a minimum time of tactmax, after RESET# is taken high.
3. VREF, data, and clock inputs must be held at valid voltage levels (not oating) for a minimum time of tinactmax, after RESET# is taken low.
REGISTER ELECTRICAL CHARACTERISTICS*
REGISTER TIMING REQUIREMENTS (note1)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3H32M64E-400SBM | 32M X 64 DDR DRAM, 0.6 ns, PBGA208 |
| W3H32M64E-667SBC | 32M X 64 DDR DRAM, 0.65 ns, PBGA208 |
| W3H32M64EA-400SBC | 32M X 64 DDR DRAM, PBGA208 |
| W3H32M64EA-667SBM | 32M X 64 DDR DRAM, PBGA208 |
| W3H32M64EA-667SBC | 32M X 64 DDR DRAM, PBGA208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H13C1048AT | 制造商:AVX 制造商全稱:AVX Corporation 功能描述:High Current Feedthry Capacitors |
| W3H13C1048AT1A | 功能描述:饋通電容器 25volt 0.1uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體: |
| W3H13C1048AT1F | 功能描述:饋通電容器 25volt 0.1uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體: |
| W3H15C1038AT | 制造商:AVX 制造商全稱:AVX Corporation 功能描述:High Current Feedthry Capacitors |
| W3H15C1038AT1A | 功能描述:饋通電容器 50volt .01uF X7R RoHS:否 制造商:Tusonix 電容:8200 pF 容差:- 20 %, + 80 % 電壓額定值: 工作溫度范圍: 溫度系數(shù): 封裝 / 箱體: |
發(fā)布緊急采購，3分鐘左右您將得到回復。