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參數(shù)資料
| 型號： | W3H64M72E-400SBIF |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, PBGA208 |
| 封裝： | 16 X 22 MM, 1 MM PITCH, LEAD FREE, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 30/32頁 |
| 文件大?。?/td> | 944K |
| 代理商： | W3H64M72E-400SBIF |
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W3H64M72E-XSBX
W3H64M72E-XSBXF
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
December 2009
2010 White Electronic Designs Corp. All rights reserved
Rev. 9
White Electronic Designs Corp. reserves the right to change products or specications without notice.
tVTD 1
CKE
Rtt
Power-up:
V dd and stable
clock (CK, CK#)
T = 200s (MIN) 3
High-Z
DM
15
DQS
15
High-Z
Address
16
CK
CK#
tCL
V tt 1
V ref
V CC Q
Command
NOP 3
PRE
T0
Ta0
Don’t care
tCL
tCK
V CC
ODT
DQ
15
High-Z
Tb0
200 cycles of CK are required before a READ command can be issued
MR with
DLL RESET
tRFC
LM 8
PRE 9
LM 7
REF 10
LM 11
Tg0
Th0
Ti0
Tj0
MR without
DLL RESET
EMR with
OCD default
Tk0
Tl0
Tm0
Te0
Tf0
EMR(2)
EMR(3)
tMRD
LM 6
LM 5
A10 = 1
tRPA
Tc0
Td0
SSTL_18
low level
2
Valid 14
Valid
Indicates a Break in
Time Scale
LM 12
EMR with
OCD exit
LM 13
Normal
operation
See no te 10
Code
A10 = 1
Code
tMRD
tRPA
tRFC
V CC L
tMRD
EMR
T = 400ns (MIN) 4
LVCMOS
low level 2
FIGURE 4 – POWER-UP AND INITIALIZATION
Notes appear on page 8
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-400SBM | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 400MHZ, 208PBGA MIL-TEMP. - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3H64M72E-533ES | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
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