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參數(shù)資料
| 型號(hào)： | W3H64M72E-533ES |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM, 0.5 ns, PBGA208 |
| 封裝： | 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 999K |
| 代理商： | W3H64M72E-533ES |
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W3H64M72E-XSBX
11
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2006
Rev. 2
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
CAS LATENCY (CL)
The CAS latency (CL) is dened by bits M4–M6, as shown
in Figure 5. CL is the delay, in clock cycles, between the
registration of a READ command and the availability of
the rst bit of output data. The CL can be set to 3, 4, 5,
or 6 clocks, depending on the speed grade option being
used.
DDR2 SDRAM does not support any half-clock latencies.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted
CAS additive latency (AL). This feature allows the READ
command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks.
Examples of CL = 3 and CL = 4 are shown in Figure 6;
both assume AL = 0. If a READ command is registered
at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n+m (this
assumes AL = 0).
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 3 (AL = 0)
READ
Burst length = 4
Posted CAS# additive latency (AL) = 0
Shown with nominal
t AC, tDQSCK, and tDQSQ
T0
T1
T2
DON’T CARE
TRANSITIONING DATA
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
DOUT
n + 3
DOUT
n + 2
DOUT
n + 1
CK
CK#
COMMAND
DQ
DQS, DQS#
CL = 4 (AL = 0)
READ
T0
T1
T2
NOP
DOUT
n
T3
T4
T5
NOP
T6
NOP
FIGURE 6 – CAS LATENCY (CL)
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| W3H64M72E-ESM | 64M X 72 DDR DRAM, PBGA208 |
| W3H64M72E-SBC | 64M X 72 DDR DRAM, PBGA208 |
| W3H64M72E-400ESC | 64M X 72 DDR DRAM, 0.6 ns, PBGA208 |
| W3H64M72E-667ES | 64M X 72 DDR DRAM, PBGA208 |
| W3HG128M64EEU534D4IMG | 128M X 64 DDR DRAM MODULE, 0.5 ns, ZMA200 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3H64M72E-533ESC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533ESM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SB | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package |
| W3H64M72E-533SBC | 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 533MHZ, 208PBGA COMMERICAL TEMP. - Bulk |
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