參數(shù)資料
型號(hào)： W3H64M72E-667ES
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： DRAM
英文描述： 64M X 72 DDR DRAM, PBGA208
封裝： 17 X 23 MM, 1 MM PITCH, PLASTIC, BGA-208
文件頁(yè)數(shù)： 9/30頁(yè)
文件大?。?/td> 999K
代理商： W3H64M72E-667ES
W3H64M72E-XSBX
17
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
December 2006
Rev. 2
ADVANCED*
White Electronic Designs Corp. reserves the right to change products or specications without notice.
DESELECT
The DESELECT function (CS# HIGH) prevents new
commands from being executed by the DDR2 SDRAM.
The DDR2 SDRAM is effectively deselected. Operations
already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct
the selected DDR2 SDRAM to perform a NOP (CS# is
LOW; RAS#, CAS#, and WE are HIGH). This prevents
unwanted commands from being registered during idle
or wait states. Operations already in progress are not
affected.
LOAD MODE (LM)
The mode registers are loaded via inputs BA2–BA0, and
A12–A0. BA2–BA0 determine which mode register will
be programmed. See “Mode Register (MR)”. The LM
command can only be issued when all banks are idle, and
a subsequent execute able command cannot be issued
until tMRD is met.
BANK/ROW ACTIVATION
ACTIVE COMMAND
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA2–BA0 inputs selects the bank, and the
address provided on inputs A12–A0 selects the row.
This row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
ACTIVE OPERATION
Before any READ or WRITE commands can be issued to
a bank within the DDR2 SDRAM, a row in that bank must
be opened (activated), even when additive latency is used.
This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated.
After a row is opened with an ACTIVE command, a READ
or WRITE command may be issued to that row, subject to
the tRCD specication. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number
to determine the earliest clock edge after the ACTIVE
command on which a READ or WRITE command can be
entered. The same procedure is used to convert other
specication limits from time units to clock cycles. For
example, a tRCD (MIN) specication of 20ns with a 266
MHz clock (tCK = 3.75ns) results in 5.3 clocks, rounded
up to 6.
A subsequent ACTIVE command to a different row in the
same bank can only be issued after the previous active
row has been closed (precharged). The minimum time
interval between successive ACTIVE commands to the
same bank is dened by tRC
A subsequent ACTIVE command to another bank can be
issued while the rst bank is being accessed, which results
in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to
different banks is dened by tRRD
FIGURE 10 – ACTIVE COMMAND
DON’T CARE
CK
CK#
CS#
RAS#
CAS#
WE#
CKE
Row
Bank
ADDRESS
BANK ADDRESS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
W3H64M72E-667ESC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667ESI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667ESM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667SB 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:64M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
W3H64M72E-667SBC 制造商:Microsemi Corporation 功能描述:64M X 72 DDR2, 1.8V, 667MHZ, 208PBGA COMMERICAL TEMP. - Bulk
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