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參數(shù)資料
| 型號： | W3HG128M64EEU806D4SG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 128M X 64 DDR DRAM MODULE, 0.45 ns, ZMA200 |
| 封裝： | ROHS COMPLIANT, SODIMM-200 |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 221K |
| 代理商： | W3HG128M64EEU806D4SG |
W3HG128M64EEU-D4
November 2006
Rev. 2
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (continued)
VCC = +1.8V ±0.1V
Data
Strobe
AC Characteristics
Symbol
806
665
534
403
Units
Notes
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
DQS–DQ skew, DQS to last DQ valid, per group, per
access
t
DQSQ
240
300
350
ps
15, 17
DQS read preamble
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
33, 37,
43
DQS read postamble
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
33, 34,
37, 43
DQS write preamble setup time
t
WPRES
0000
ps
12, 13,
DQS write preamble
t
WPRE
0.35
0.25
tCK
37
DQS write postamble
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
11, 37
Write command to rst DQS latching transition
tDQSS
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
WL-
0.25
WL+
0.25
tCK
37
Command
and
Address
Address and control input pulse width for each input
t
IPW
0.6
tCK
37
Address and control input setup time
t
ISa
400
500
600
ps
6, 19
Address and control input hold time
t
IHa
400
500
600
ps
6, 19
Address and control input setup time
t
ISb
200
250
350
ps
6, 19
Address and control input hold time
t
IHb
275
375
475
6, 19
CAS# to CAS# command delay
t
CCD
2222
tCK
37
ACTIVE to ACTIVE (same bank) command
t
RC
54
55
ns
31, 37
ACTIVE bank a to ACTIVE bank b command
t
RRD
(x8)
7.5
ns
25, 37
ACTIVE to READ or WRITE delay
t
RCD
12
15
ns
37
Four Bank Activate period
t
FAW
(x8)
37.5
ns
28, 37
ACTIVE to PRECHARGE command
t
RAS
40 70,000 40 70,000 40 70,000 40 70,000
ns
18, 31,
37
Internal READ to precharge command delay
t
RTP
7.5
ns
21, 25.
37
Write recovery time
t
WR
15
ns
25, 37
Auto precharge write recovery + precharge time
t
DAL
tWR + tRP
ns
20
Internal WRITE to READ command delay
t
WTR
7.5
10
ns
25, 37
PRECHARGE command period
t
RP
12
15
ns
29, 37
PRECHARGE ALL command period
t
RPA
tRP + tCK
ns
29
LOAD MODE command cycle time
t
MRD
2222
tCK
37
Note:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG128M64EEU806D4XXG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEU-D4 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEUXXXD4IMG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEUXXXD4ISG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
| W3HG128M64EEUXXXD4MG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:1GB - 128Mx64 DDR2 SDRAM UNBUFFERED, SO-DIMM |
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