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參數(shù)資料
| 型號： | W3HG128M72AEF534F1GCG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | DDR DRAM MODULE, DMA240 |
| 封裝： | ROHS COMPLIANT, FBDIMM-240 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG128M72AEF534F1GCG |
8
W3HG128M72AEF-Fx
September 2007
Rev. 3
ADVANCED
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Units
Notes
VIN, VOUT
Voltage on any pin relative to VSS
-0.3
1.75
V
VCC
Voltage on VCC pin relative to VSS
-0.3
1.75
V
VDD
Voltage VCC pin relative to VSS
-0.5
2.3
V
VTT
Voltage on VTT pin relative to VSS
-0.5
2.3
V
TSTG
Storage temperature
-55
100
°C
TCASE
DDR2 SDRAM device operating temperature (Ambient)
0
95
°C
1, 2
AMB device operating temperature (Ambient)
0
110
°C
Stresses greater than those listed in absolute maximum rating table may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specication is not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
NOTES:
1. TCASE is specied at 95°C only when using 2X refresh timing (tREFI = 7.8μs at or below 85°C; tREFI = 3.9μs above 85°C);.DDR2 SDRAM component datasheet, though the
FBDIMM does not have an IT option.
2. See applicable DDR2 SDRAM component datasheet for tREFI and extended mode register setting. The tREFIIT parameter is used to specify the doubled refresh interval
neceassary to sustain 95°C operation; however, the FBDIMM does not have an IT option.
INPUT DC VOLTAGE AND OPERATING CONDITIONS
Symbol
Parameter
Min
Nom
Max
Units
Notes
VCC
AMB supply voltage
1.455
1.50
1.575
V
VDD
DDR2 SDRAM supply voltage
1.7
1.8
1.9
V
VTT
Termination voltage
0.48 x VDD
0.50 x VDD
0.52 x VDD
V
VDDSPD
SPD supply voltage
3.0
3.3
3.6
V
VIH(DC)
SPD Input HIGH (logic 1) voltage
2.1
VDDSPD
V1
VIL(DC)
SPD Input LOW (logic 0) voltage
0.8
V
1
VIH(DC)
RESET Input HIGH (logic 1) voltage
1.0
V
2
VIL(DC)
RESET Input LOW (logic 0) voltage
0.5
V
1
IL
Leakage Current (RESET)
-90
90
μA2
IL
Leakage Current (link)
-5
5
μA3
NOTES:
1. Applies for SMB and SPD bus signals.
2. Applies for AMB CMOS signal RESET#.
3. For all other AMB related DC parameters, please refer to the high-speed differential link interface specication.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG2128M72ACER403AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER534AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER665AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER806AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER-AD6 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
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