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參數(shù)資料
| 型號： | W3HG2128M64EEU665XD4SG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 256M X 64 DDR DRAM MODULE, 0.45 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-DIMM-200 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 188K |
| 代理商： | W3HG2128M64EEU665XD4SG |
W3HG2128M64EEU-D4
January 2008
Rev. 7
10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
AC CHARACTERISTICS
SYMBOL
805
806
665
534
403
UNIT
PARAMETER
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Command
and
Address
ACTIVE to ACTIVE (same bank) command
tRC
57.5
60
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
12.5
15
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
45
70,000
45
70,000
45
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
7.5
ns
Write recovery time
tWR
15
ns
Auto precharge write recovery + precharge
time
tDAL
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
tWR +
tRP
ns
Internal WRITE to READ command delay
tWTR
7.5
10
ns
PRECHARGE command period
tRP
12.5
15
ns
LOAD MODE command cycle time
tMRD
22222
tCK
CKE low to CK,CK# uncertainty
tDELAY
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
tIS + tCK
+ tIH
ns
Self
Refresh
REFRESH to Active of Refresh to Refresh
command interval
tRFC
105
ns
Average periodic refresh interval
tREFI
7.8
μs
Exit self refresh to non-READ command
tXSNR
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
tRFC (MIN)
+ 10
ns
Exit self refresh to READ command
tXSRD
200
tCK
ODT
ODT turn-on delay
tAOND
2222222222
tCK
ODT turn-on
tAON
tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 700
tAC
(MIN)
tAC
(MAX)
+ 1000
tAC
(MIN)
tAC
(MAX)
+ 1000
ps
ODT turn-off delay
tAOFD
2.5
tCK
ODT turn-off
tAOF
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
tAC
(MIN)
tAC
(MAX)
+ 600
ps
ODT turn-on (power-down mode)
tAONPD
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2 x tCK
+ tAC
(MAX)
+ 1000
ps
ODT turn-off (power-down mode)
tAOFPD
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
tAC
(MIN)
+ 2000
2.5
x tCK
+ tAC
(MAX)
+ 1000
ps
ODT to power-down entry latency
tANPD
33333
tCK
ODT power-down exit latency
tAXPD
88888
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
22222
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
8-AL
8 - AL
7 - AL
6 - AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
22222
tCK
CKE minimum high/low time
tCKE
33333
tCK
AC specication is based on
SAMSUNG components. Other DRAM manufactures specication may be different.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W3HG2128M64EEU665XD4ISG | 256M X 64 DDR DRAM MODULE, 0.45 ns, ZMA200 |
| W3HG2128M64EEU806XD4SG | 256M X 64 DDR DRAM MODULE, 0.4 ns, DMA200 |
| W3HG2128M64EEU403XD4MG | SYNCHRONOUS DRAM MODULE, DMA200 |
| W3HG2128M64EEU534XD4MG | SYNCHRONOUS DRAM MODULE, DMA200 |
| W3HG2128M64EEU806D4ISG | 256M X 64 DDR DRAM MODULE, 0.4 ns, DMA200 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG2128M72ACER403AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER534AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER665AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
| W3HG2128M72ACER806AD6XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:2GB - 2x128Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP |
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