參數(shù)資料
型號(hào): W3HG2256M72ACER534D6ISG
廠商: WHITE ELECTRONIC DESIGNS CORP
元件分類(lèi): DRAM
英文描述: 512M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁(yè)數(shù): 9/12頁(yè)
文件大小: 0K
代理商: W3HG2256M72ACER534D6ISG
WV3HG2256M72AER-D6
ADVANCED
6
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
October 2006
Rev. 2
DDR2 ICC SPECIFICATIONS AND CONDITIONS
VCC = +1.8V ± 0.1V
Symbol Proposed Conditions
806
665
534
403
Units
ICC0*
Operating one bank active-precharge current;
tCK = tCK(ICC), tRC = tRC(ICC), tRAS = tRASmin(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
2,336
2,246
2,156
mA
ICC1*
Operating one bank active-read-precharge current;
IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRC = tRC (ICC), tRAS = tRASmin(ICC), tRCD =
tRCD(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as ICC4W
TBD
2,516
2,426
2,336
mA
ICC2P**
Precharge power-down current;
All banks idle; tCK = tCK(ICC); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
TBD
932
mA
ICC2Q**
Precharge quiet standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
TBD
1,940
1,760
mA
ICC2N**
Precharge standby current;
All banks idle; tCK = tCK(ICC); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
TBD
2,120
1,940
mA
ICC3P**
Active power-down current;
All banks open; tCK = tCK(ICC); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
TBD
1,580
1,400
mA
Slow PDN Exit MRS(12) = 1
TBD
932
mA
ICC3N**
Active standby current;
All banks open; tCK = tCK(ICC), tRAS = tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
TBD
2,300
2,120
mA
ICC4W*
Operating burst write current;
All banks open, Continuous burst writes; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data bus inputs are SWITCHING
TBD
3,056
2,876
2,516
mA
ICC4R*
Operating burst read current;
All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = 0; tCK = tCK(ICC), tRAS =
tRASmax(ICC), tRP = tRP(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as ICC4W
TBD
3,056
2,876
2,516
mA
ICC5B**
Burst auto refresh current;
tCK = tCK(ICC); Refresh command at every tRFC(ICC) interval; CKE is HIGH, CS# is HIGH between valid
commands; Other control and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
TBD
8,420
8,240
8,060
mA
ICC6**
Self refresh current;
CK and CK# at 0V; CKE 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING
Normal
TBD
360
mA
ICC7*
Operating bank interleave read current;
All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(ICC), AL = tRCD(ICC)-1*tCK(ICC); tCK = tCK(ICC),
tRC = tRC(ICC), tRRD = tRRD(ICC), tRCD = 1*tCK(ICC); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are STABLE during DESELECTs; Data pattern is same as ICC4R; Refer to the
following page for detailed timing conditions
TBD
6,116
5,756
5,396
mA
Note:
ICC specs are based on
SAMSUNG components. Other DRAM manufacturers parameters may be different.
* Value calculated as one module rank in this operation condition, and all other module ranks in ICC2P (CKE LOW) mode.
** Value calculated reects all module ranks in the operating condition.
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