參數(shù)資料
型號: W3HG2256M72ACER534D6SG
廠商: MICROSEMI CORP-PMG MICROELECTRONICS
元件分類: DRAM
英文描述: 512M X 72 DDR DRAM MODULE, 0.5 ns, DMA240
封裝: ROHS COMPLIANT, DIMM-240
文件頁數(shù): 11/12頁
文件大?。?/td> 0K
代理商: W3HG2256M72ACER534D6SG
WV3HG2256M72AER-D6
ADVANCED
8
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
October 2006
Rev. 2
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION (Continued)
VCC = +1.8V ± 0.1V
AC Characteristics
806
665
534
403
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Data
Strobe
DQS read preamble
tRPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS write preamble setup time
tWPRES
TBD
000
ps
DQS write preamble
tWPRE
TBD
0.35
tCK
DQS write postamble
tWPST
TBD
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write command to rst DQS latching
transition
tDQSS
TBD
WL-0.25
WL+0.25
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Command
and
Address
Address and control input pulse width
for each input
tIPW
TBD
0.6
tCK
Address and control input setup time
tISa
TBD
200
250
350
ps
Address and control input hold time
tIHa
TBD
275
375
475
ps
CAS# to CAS# command delay
tCCD
TBD
222
tCK
Active to Active (same bank) command
tRC
TBD
54
55
ns
Active bank a to Active b bank
command
tRRD
TBD
7.5
ns
Active to Read or Write delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ns
Active to precharge command
tRAS
TBD
39
70,000
40
70,000
40
70,000
ns
Internal Read to precharge command
delay
tRTP
TBD
7.5
ns
Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery and
precharge time
tDAL
TBD
tWR+tRP
ns
Interval Write to Read command delay
tWTR
TBD
7.5
10
ns
Precharge command period
tRP
TBD
15
ns
Precharge All command period
tRPA
TBD
tRP+tCK
ns
Load Mode command cycle time
tMRD
TBD
222
tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS+tCK
+
tIH
tIS+tCK
+
tIH
tIS+tCK
+
tIH
ns
Note:
AC specication is based on
SAMSUNG components. Other DRAM manufactures specication may be different.
Continued on next page
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