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參數(shù)資料
| 型號： | W3HG32M72EER534AD7MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 DDR DRAM MODULE, 0.5 ns, DMA244 |
| 封裝： | ROHS COMPLIANT, MINI-DIMM-244 |
| 文件頁數(shù)： | 9/14頁 |
| 文件大?。?/td> | 195K |
| 代理商： | W3HG32M72EER534AD7MG |
W3HG32M72EER-AD7
December 2005
Rev. 0
ADVANCED
4
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
VCC
1 .7
1 .8
1 .9
V
1
I/O Supply voltage
VCCQ
1 .7
1 .8
1 .9
V
4
VCCL Supply voltage
VCCL
1 .7
1 .8
1 .9
V
4
I/O Reference voltage
VREF
0.49 x VCCQ
0.50 x VCCQ
0.51 x VCCQ
V2
I/O Termination voltage
VTT
VREF-0.04
VREF
VREF + 0.04
V
3
Notes:
1. VCC and VCCQ must track each other. VCCQ must be less than or equal to VCC.
2. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not excedd ±1 percent of the DC
value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
4. VCCQ tracks with VCC; VCCL track with VCC.
ABSOLUTE MAXIMUM DC RATINGS
Symbol
Parameter
MIN
MAX
U nit
VCC
Voltage on VCC pin relative to VSS
-1.0
2.3
V
VCCQ
Voltage on VCCQ pin relative to VSS
-0.5
2.3
V
VCCL
Voltage on VCCL pin relative to VSS
-0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.5
2.3
V
TSTG
Storage temperature
-55
100
°C
TCASE
Device operating temperature
0
85
°C
TOPR
Operating temperature (ambient)
0
55
°C
IL
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V<VIN<0.95V; Other pins not under test = 0V
Command/Address,
RAS#, CAS#, WE#,
CS#, CKE
-5
5
A
CK, CK#
-5
5
A
DM
-5
5
A
IOZ
Output leakage current;
0V<VOUT<VCCQ; DQs and ODT are disable
DQ, DQS, DQS#
-5
5
A
IVREF
VREF leakage current; VREF = Valid VREF level
-18
18
A
INPUT/OUTPUT CAPACITANCE
TA=25 0 C, f=1 00MHz
Parameter
Symbol
Min
Max
Unit
Input capacitance (A0 - A12, BA0 - BA1 ,RAS#,CAS#,WE#)
CIN1
pF
Input capacitance ( CKE0), (ODT0)
CIN2
pF
Input capacitance (CS0#)
CIN3
pF
Input capacitance (CK0, CK0#)
CIN4
pF
Input capacitance (DM0 - DM8), (DQS0 - DQS8)
CIN5
pF
Input capacitance (DQ0 - DQ63), (CB0 - CB7)
COUT1
pF
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