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參數(shù)資料
| 型號： | W3HG64M72EER403PD4MG |
| 廠商： | MICROSEMI CORP-PMG MICROELECTRONICS |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.6 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-RDIMM-200 |
| 文件頁數(shù)： | 2/13頁 |
| 文件大?。?/td> | 249K |
| 代理商： | W3HG64M72EER403PD4MG |
W3HG64M72EER-PD4
February 2007
Rev. 0
10
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONT AC TIMING PARAMETERS & SPECIFICATIONS (cont'd)
VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
665
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Command
and
Address
ACTIVE to ACTIVE (same bank) command
tRC
TBD
60
55
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
TBD
7.5
ns
ACTIVE to READ or WRITE delay
tRCD
TBD
15
ns
Four Bank Activate period
tFAW
TBD
37.5
ns
ACTIVE to PRECHARGE command
tRAS
TBD
40
70,000
40
70,000
40
70,000
ns
Internal READ to precharge command delay
tRTP
TBD
7.5
ns
Write recovery time
tWR
TBD
15
ns
Auto precharge write recovery + precharge
time
tDAL
TBD
tWR+tRP
ns
Internal WRITE to READ command delay
tWTR
TBD
7.5
10
ns
PRECHARGE command period
tRP
TBD
15
ns
PRECHARGE ALL command period
tRPA
TBD
tRP+tCK
ns
LOAD MODE command cycle time
tMRD
TBD
22
2
tCK
CKE low to CK,CK# uncertainty
tDELAY
TBD
tIS+tCK
tIH
tIS+tCK
tIH
tIS+tCK
tIH
ns
Self
Refresh
REFRESH to Active of Refresh to Refresh
command interfal
tRFC
TBD
105
70,000
105
70,000
105
70,000
ns
Average periodic refresh interval
tREFI
TBD
7.8
μs
Exit self refresh to non-READ command
tXSNR
TBD
tRFC(MIN)
+10
tRFC(MIN)
+10
tRFC(MIN)
+10
ns
Exit self refresh to READ command
tXSRD
TBD
200
tCK
Exit self refresh timing reference
tISXR
TBD
tIS
ps
ODT
ODT turn-on delay
tAOND
TBD
2
22222
tCK
ODT turn-on
tAON
TBD
tAC(MIN)
tAC(MAX)
+1000
tAC(MIN)
tAC(MAX)
+1000
tAC(MIN)
tAC(MAX)
+1000
ps
ODT turn-off delay
tAOFD
TBD
2.5
tCK
ODT turn-off
tAOF
TBD
tAC(MIN)
tAC(MAX)
+600
tAC(MIN)
tAC(MAX)
+600
tAC(MIN)
tAC(MAX)
+600
ps
ODT turn-on (power-down mode)
tAONPD
TBD
tAC(MIN)
+2000
2 x tCK+
tAC(MIN)
+1000
tAC(MIN)
+2000
2 x tCK+
tAC(MIN)
+1000
tAC(MIN)
+2000
2 x tCK+
tAC(MIN)
+1000
ps
ODT turn-off (power-down mode)
tAOFPD
TBD
tAC(MIN)
+2000
2.5 x
tCK+
tAC(MIN)
+1000
tAC(MIN)
+2000
2.5 x
tCK+
tAC(MIN)
+1000
tAC(MIN)
+2000
2.5 x
tCK+
tAC(MIN)
+1000
ps
ODT to power-down entry latency
tANPD
TBD
33
3
tCK
ODT power-down exit latency
tAXPD
TBD
88
8
tCK
Power-Down
Exit active power-down to READ command,
MR[bit12=0]
tXARD
TBD
22
2
tCK
Exit active power-down to READ command,
MR[bit12=1]
tXARDS
TBD
7-AL
6-AL
tCK
A Exit precharge power-down to any non-
READ command.
tXP
TBD
22
2
tCK
CKE minimum high/low time
tCKE
TBD
33
3
tCK
* AC specication is based on
SAMSUNG components. Other DRAM manufactures specication may be different.
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