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參數(shù)資料
| 型號： | W3HG64M72EER665PD4IMG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.45 ns, DMA200 |
| 封裝： | ROHS COMPLIANT, SO-RDIMM-200 |
| 文件頁數(shù)： | 8/13頁 |
| 文件大?。?/td> | 249K |
| 代理商： | W3HG64M72EER665PD4IMG |
W3HG64M72EER-PD4
February 2007
Rev. 0
4
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
VCC
Voltage on VCC pin relative to VSS
-0.5
2.3
V
VIN, VOUT
Voltage on any pin relative to VSS
-0.5
2.3
V
TSTG
Storage Temperature
-55
100
°C
IL
Input leakage current; Any input 0V<VIN<VCC; VREF input
0V,VIN,0.95V; Other pins not under test = 0V
Command/Address,
RAS#, CAS#, WE#,
-5
5
μA
CK, CK#
-10
10
μA
DM
-5
5
μA
IOZ
Output leakage current; 0V<VIN<VCC; DQs and ODT are disable
DQ, DQS, DQS#
-5
5
μA
IVREF
VREF leakage current; VREF = Valid VREF level
-18
18
μA
DC OPERATING CONDITIONS
All voltages referenced to VSS
Parameter
Symbol
Min
Typical
Max
Unit
Notes
Supply Voltage
VCC
1.7
1.8
1.9
V
3
I/O Reference Voltage
VREF
0.49 x VCC
0.50 x VCC
0.51 x VCC
V1
I/O Termination Voltage
VTT
VREF-0.04
VREF
VREF+0.04
V
2
SPD Supply Voltage
VCCSPD
1.7
-
3.6
V
Notes:
1
VREF is expected to equal VCC/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-1 percent of the
DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This measurement is to be taken at the nearest VREF bypass capacitor.
2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. VCCQ of all IC's are tied to VCC.
OPERATING TEMPERATURE CONDITION
Parameter
Symbol
Rating
Units
Notes
Operating Case Temperature (Commercial)
TOPER
0 to +85°C
°C
1, 2
NOTE:
1. Operation temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JEDEC JESD51.2
2. At 0 to +85
°C, operation temperature range, all DRAM specication will be supported.
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