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參數(shù)資料
| 型號： | W3HG64M72EER806AD7MG |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, ZMA244 |
| 封裝： | ROHS COMPLIANT, DIMM-244 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 256K |
| 代理商： | W3HG64M72EER806AD7MG |
W3HG64M72EER-AD7
October 2006
Rev. 2
ADVANCED
7
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
DDR2 SDRAM COMPONENT AC TIMING PARAMETERS & SPECIFICATION
0°C ≤ TCASE < +85°C; VCCQ = + 1.8V ± 0.1V, VCC = +1.8V ± 0.1V
AC CHARACTERISTICS
806
667
534
403
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
Notes
Clock
Clock cycle time
CL = 6
tCK (6)
TBD
ps
16, 24
CL = 5
tCK (5)
TBD
3,000
8,000
ps
16, 24
CL = 4
tCK (4)
TBD
3,750
8,000
3,750
8,000
5,000
8,000
ps
16, 24
CL = 3
tCK (3)
TBD
5,000
8,000
5,000
8,000
5,000
8,000
ps
16, 24
CK high-level width
tCH
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
18
CK low-level width
tCL
TBD
0.45
0.55
0.45
0.55
0.45
0.55
tCK
18
Half clock period
tHP
TBD
MIN
(tCH,
tCL)
MIN
(tCH,
tCL)
MIN
(tCH,
tCL)
ps
19
Data
DQ output access time from CK/CK#
tAC
TBD
-450
+450
-500
+500
-600
+600
ps
Data-out high-impedance window from
CK/CK#
tHZ
TBD
tAC
(MAX)
tAC
MAX
tAC
MAX
ps
8, 9
Data-out low-impedance window from CK/CK#
tLZ
TBD
tAC
(MIN)
tAC
(MAX)
tAC
(MIN)
tAC
(MAX)
tAC
(MIN)
tAC
(MAX)
ps
8, 10
DQ and DM input setup time relative to DQS
tDSa
TBD
300
350
400
ps
7, 15,
21
DQ and DM input hold time relative to DQS
tDHa
TBD
300
350
400
ps
7, 15,
21
DQ and DM input setup time relative to DQS
tDSb
TBD
100
150
tCK
7, 15,
21
DQ and DM input hold time relative to DQS
tQHb
TBD
175
225
275
ps
7, 15,
21
DQ - DQS hold, DQS to rst DQ to go
nonvalid, per access relative to DQS
tDIPW
TBD
0.35
ps
Data hold skew factor
tQHS
TBD
340
400
450
DQ - DQS hold, DQS to rst DQ to go
nonvalid, per access
tQH
TBD
tHP-
tQHS
tHP-
tQHS
tHP-
tQHS
15, 17
Data valid output window (DVW)
tDVW
TBD
tQH-
tDQSQ
tQH-
tDQSQ
tQH-
tDQSQ
15, 17
Data
Strobe
DQS input high pulse width
tDQSH
TBD
0.35
tCK
DQS input low pulse width
tDQSL
TBD
0.35
tCK
DQS output access time from CK/CK#
tDQSCK
TBD
-400
+400
-450
+450
-500
+500
ps
DQS falling edge to CK rising– setup time
tDSS
TBD
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
TBD
0.2
tCK
DQS - DQ skew, DQS to last DQ valid, per
group, per access
tDQSQ
TBD
240
300
350
ps
15, 17
DQS read preamble
tRPRE
TBD
0.9
1.1
0.9
1.1
0.9
1.1
tCK
35
NOTE:
AC specication is based on
MICRON components. Other DRAM manufactures specication may be different.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W3HG64M72EER806AD7XG | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3HG64M72EER-AD7 | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:512MB - 64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM |
| W3J128M72G-1066PBI | 制造商:Microsemi Corporation 功能描述:DRAM MODULE DDR3 SDRAM 9G-BIT - Bulk 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3J128M72G-800PBI | 制造商:Microsemi Corporation 功能描述:SDRAM MEMORY |
| W3J512M72G-1333PBI | 制造商:Microsemi Corporation 功能描述:512MX72 DDR3, 1333MHZ, I-TEMP OPERATING RANGE - Bulk |
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