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參數(shù)資料
| 型號(hào)： | W528S08 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大小： | 108K |
| 代理商： | W528S08 |
W528XXX
Publication Release Date: March 1999
- 11 - Revision A1
b.
Level-Hold Trigger Mode
0:
LD EN, 0x11
; Enable TG1 rising/falling edge input.
H4 + sound1 + T4
JP 0
; Repeat sound1 until TG1 key released.
4:
END
; As soon as TG1 key is released, execute this group entry.
The timing diagram is shown below:
TG1:
AUD:
Stop Immediately
Sound 1
case 1:
case 2:
TG1:
AUD:
Stop Immediately
c.
Complete-Cycle Level Hold
0:
LD EN, 0x01
; Enable TG1 falling edge only.
H4 + sound1 + T4
JP 0 @TG1_LOW
; If TG1 status is low level voltage (trigger is pressed), then j ump
to 0;
if not, execute next instruction (END).
END
The timing diagram is shown below:
AUD:
TG1:
Sound 1
case 1:
case 2:
TG1:
AUD:
Sound 1
Sound 1
d.
Single-Cycle Level Hold
0:
LD EN, 0x11
; Enable both falling and rising edge input of TG1.
H4 + sound1 + T4
END
4: END
; As soon as TG1 is key released, execute this group entry.
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