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參數(shù)資料
| 型號： | W532 |
| 英文描述： | Clocks and Buffers |
| 中文描述： | 時鐘和緩沖器 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 114K |
| 代理商： | W532 |
Frequency Multiplying, Peak Reducing EMI Solution
Table 1. Output Frequency Range Selection
W532
Cypress Semiconductor Corporation
Document #: 38-07253 Rev. *A
3901 North First Street
San Jose
CA 95134
Revised December 28, 2002
408-943-2600
Features
Cypress PREMIS family offering
Generates an EMI optimized clocking signal at the
output
Selectable frequency range and multiplication factor
Single 1.25% or 5% center spread output
Integrated loop filter components
Operates with a 3.3V or 5V supply
Low power CMOS design
Available in 16-pin SOIC
Key Specifications
Supply Voltages:........................................V
DD
= 3.3V ±0.3V
or V
DD
= 5V ±10%
Frequency Range: .........................15 MHz
≤
F
out
≤
120 MHz
Cycle to Cycle Jitter: .........................................150 ps (typ.)
Output Duty Cycle: ............................... 40/60% (worst case)
Output Rise and Fall Time ...................................5 ns (max.)
PREMIS is a trademark of Cypress Semiconductor.
OR2
0
0
1
1
OR1
0
1
0
1
Output Range
(Multiplication Factor Selection)
reserved
15 MHz
≤
F
IN
≤
30 MHz
30 MHz
≤
F
IN
≤
60 MHz
60 MHz
≤
F
IN
≤
120 MHz
Table 2. Modulation Width Selection
MW
0
1
Output
F
avg
+
0.625%
≥
F
out
≥
F
avg
–
0.625%
F
avg
+
2.5%
≥
F
out
≥
F
avg
–
2.5%
Table 3. Input Frequency Range Selection
IR2
0
0
1
1
IR1
0
1
0
1
Input Range
reserved
15 MHz
≤
F
IN
≤
30 MHz
30 MHz
≤
F
IN
≤
60 MHz
60 MHz
≤
F
IN
≤
120 MHz
Simplified Block Diagram
Pin Configuration
SOIC
Spread Spectrum
Output
W532
(EMI suppressed)
3.3V or 5.0V
Oscillator or
Reference Input
Spread Spectrum
W532
(EMI suppressed)
3.3V or 5.0V
XTAL
X1
X2
X1
W
16
15
14
13
12
1
2
3
4
5
6
7
8
X1
X2
AVDD
*OR1
NC
AGND
^OR2
*SSON#
VDD
GND
IR1^
IR2^
SSOUT
GND
10
11
9
VDD
MW*
Notes:
1.
2.
^ pins have internal pull-up
* pins have internal pull-down
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