![](http://datasheet.mmic.net.cn/230000/W536020K_datasheet_15630954/W536020K_5.png)
Publication Release Date:Nov 2000
- 5 - Revision A1
ROSC
I
Connect resistor to VDD pad to generate speech or melody playing clock source.
PWM1/DAC
O
While speech or melody is active, PWM1/DAC is speaker direct driving output or
DAC output controlled by voice output file.
PWM2
O
While speech or melody is active, PWM2 is another speaker direct driving output.
WRP (5)
O
External serial memory address write clock for voice extension (W536120K only).
RDP (5)
O
External serial memory address read clock for voice extension. (W536120K only).
SPDATA (5)
I/O
External serial memory data in/out for voice extension (W536120K only).
SEG0
SEG15
O
Dedicated LCD segment output pads.
SEG16/PORTN.0
SEG19/PORTN.3
SEG20/PORTM.0
SEG23/PORTM.3
SEG24/PORTL.0
SEG27/PORTL.3
SEG28/PORTK.0
SEG31/PORTK.3
SEG32/PORTJ.0
SEG35/PORTJ.3
O/O
LCD segment output pads, and can be shared as general output by register
LCDM3 bit 1. Default function is segment pad.
O/I
LCD segment output pads, and can be shared as general input by register
LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD
waveform abnormal.
O/O
LCD segment output pads, and can be shared as general output by register
LCDM2 bit 0. Default function is segment pad.
O/I
LCD segment output pads, and can be shared as general input by register
LCDM2 bit 1. Default function is segment pad and PM5.0=0 to inhibit LCD
waveform abnormal.
O/IO
LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 2. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.3=0 to inhibit LCD
waveform abnormal.
SEG36/PORTI.0
SEG39/PORTI.3
O/IO
LCD segment output pads, and can be shared as general input/output by register
LCDM2 bit 3. PM4 register is used to select input or output while shared I/O
function is active. Default function is segment pad and PM4.2=0 to inhibit LCD
waveform abnormal.
COM0
COM3
O
LCD common signal output pads either 1/8 duty or 1/4duty. The LCD frame rate
is controlled by LCDM1 register, and default value LCDM1=0111b with 64Hz
frame rate.
COM4/PORTO.0
COM7/PORTO.3
DH1, DH2 (6)
O/I
LCD common signal output pads, or shared as general input by register LCDM3.2
when in 1/4 duty mode. Default function is common function and PM5.2=0 to
inhibit LCD waveform abnormal.
O
Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects
to capacitor positive node and DH1 negative node if polar capacitor is used.
VHI
I
Connect to V6 (LCD's VLCD) or VDD which has higher voltage, to make sure there is no
any abnormal leakage current appearance.