參數(shù)資料
型號： W65C816S8PL-14
元件分類： 16位微控制器
英文描述： 16-Bit Microprocessor
中文描述： 16位微處理器
文件頁數(shù)： 53/62頁
文件大?。?/td> 891K
代理商： W65C816S8PL-14
WESTERN DESIGN CENTER
W65C816S
March 1, 2000
53
When in the Native mode, the Stack may use memory locations 000000 to 00FFFFF. The effective address
of Stack, Stack Relative, and Stack Relative Indirect Indexed addressing modes will always be within this
range. In the Emulation mode, the Stack address range is 000100 to 0001FF. The following OpCodes and
addressing modes will increment or decrement beyond this range when accessing two or three bytes: JSL,
JSR(a,x), PEA, PEI, PER, PHD, PLD, RTL
7.2
Direct Addressing
7.2.1
The Direct Addressing modes are often used to access memory registers and pointers. The
effective address generated by Direct; Direct,X and Direct,Y addressing modes will always
be in the Native mode range 000000 to 00FFFF. When in the Emulation mode, the direct
addressing range is 000000 to 0000FF, except for [Direct] and [Direct],Y addressing
modes and the PEI instruction which will increment from 0000FE or 0000FF into the Stack
area.
When in the Emulation mode and DH is not equal to zero, the direct addressing range is
00DH00 to 00DHFF, except for [Direct] and [Direct],Y addressing modes and the PEI
instruction which will increment from 00DHFE or 00DHFF into the next higher page.
When in the Emulation mode and DL in not equal to zero, the direct addressing range is
000000 to 00FFFF.
7.2.2
7.2.3
7.3
Absolute Indexed Addressing
The Absolute Indexed addressing modes are used to address data outside the direct addressing range. The
W65C02S addressing range is 0000 to FFFF. Indexing from page FFXX may result in a 00YY data fetch
when using the W65C02S. In contrast, indexing from page ZZFFXX may result in ZZ+1,00YY when
using the W65C816S.
7
.4
ABORTB Input
7.4.1
ABORTB should be held low for a period not to exceed one cycle. Also, if ABORTB is
held low during the Abort Interrupt sequence, the Abort Interrupt will be aborted. It is not
recommended to abort the Abort Interrupt. The ABORTB internal latch is cleared during
the second cycle of the Abort Interrupt. Asserting the ABORTB input after the following
instruction cycles will cause registers to be modified:
7.4.1.1
Read-Modify-Write: Processor status modified if ABORTB is asserted after a
modify cycle.
7.4.1.2
RTI: Processor status modified if ABORTB is asserted after cycle 3.
7.4.1.3
IRQB, NMIB, ABORTB BRK, COP: When ABORTB is asserted after cycle 2,
PBR and DBR will become 00 (Emulation mode) or PBR will become 00 (Native
mode).
The ABORT Interrupt has been designed for virtual memory systems. For this reason,
asynchronous ABORTB's may cause undesirable results due to the above conditions.
7.4.2
相關PDF資料
PDF描述
W65C816S8Q-14 16-Bit Microprocessor
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W65C816SP-14 16-Bit Microprocessor
W65C816SPL10 Microprocessor
W65C816SPL-14 16-Bit Microprocessor
相關代理商/技術參數(shù)
參數(shù)描述
W65C816S8Q-14 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
W65C816SP10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
W65C816SP-14 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
W65C816SPL10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Microprocessor
W65C816SPL-14 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microprocessor
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