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| 型號： | W65C816SP-14 |
| 元件分類： | 16位微控制器 |
| 英文描述： | 16-Bit Microprocessor |
| 中文描述： | 16位微處理器 |
| 文件頁數(shù)： | 16/62頁 |
| 文件大小： | 891K |
| 代理商： | W65C816SP-14 |
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WESTERN DESIGN CENTER
W65C816S
March 1, 2000
16
2.3
Bus Enable (BE)
The Bus Enable input signal allows external control of the Address and Data Buffers, as well as the RWB signal.
With Bus Enable high, the RWB and Address Buffers are active. The Data/Address Buffers are active during
the first half of every cycle and the second half of a write cycle. When BE is low, these buffers are disabled. Bus
Enable is an asynchronous signal.
2.4
Data/Address Bus (D0-D7/BA7)
These eight lines multiplex address bits BA0-BA7 with the data value. The address is present during the first
half of a memory cycle, and the data value is read or written during the second half of the memory cycle. Two
memory cycles are required to transfer 16-bit values. These lines may be set to the high impedance state by the
Bus Enable (BE) signal.
2.5
Emulation Status (E)
The Emulation Status output reflects the state of the Emulation (E) mode flag in the Processor Status (P)
Register. This signal may be thought of as an OpCode extension and used for memory and system management.
2.6
Interrupt Request (IRQB)
The Interrupt Request input signal is used to request that an interrupt sequence be initiated. When the IRQB
Disable (I) flag is cleared, a low input logic level initiates an interrupt sequence after the current instruction is
completed. The Wait-for-Interrupt (WAI) instruction may be executed to ensure the interrupt will be recognized
immediately. The Interrupt Request vector address is 00FFFE,F (Emulation mode) or 00FFEE,F (Native mode).
Since IRQB is a level-sensitive input, an interrupt will occur if the interrupt source was not cleared since the last
interrupt. Also, no interrupt will occur if the interrupt source is cleared prior to interrupt recognition. The IRQB
signal going low causes 3 bytes of information to be pushed onto the stack before jumping to the interrupt
handler. The first byte is the high byte in the Program Counter. The second byte is the Program Counter low
byte. The third byte is the status register valve. These valves are used to return the processor to it's original state
prior to the IRQ interrupt.
2.7
Memory Lock (MLB)
The Memory Lock output may be used to ensure the integrity of Read-Modify-Write instructions in a
multiprocessor system. Memory Lock indicates the need to defer arbitration of the next bus cycle. Memory Lock
is low during the last three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
referencing instructions, depending on the state of the M flag.
2.8
Memory/Index Select Status (MX)
This multiplexed output reflects the state of the Accumulator (M) and Index (X) elect flags (bits 5 and 4 of the
Processor Status (P) Register. Flag M is valid during the Phase 2 clock negative transition and Flag X is valid
during he Phase 2 clock positive transition. These bits may be thought of as OpCode extensions and may be used
for memory and system management.
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