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參數(shù)資料
| 型號： | W65C816SPL-14 |
| 元件分類： | 16位微控制器 |
| 英文描述： | 16-Bit Microprocessor |
| 中文描述： | 16位微處理器 |
| 文件頁數(shù)： | 55/62頁 |
| 文件大?。?/td> | 891K |
| 代理商： | W65C816SPL-14 |
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WESTERN DESIGN CENTER
W65C816S
March 1, 2000
55
7.11
Switching Modes
When switching from the Native mode to the Emulation mode, the X and M bits of the Status Register are
set high (logic 1), the high byte of the Stack is set to 01, and the high bytes of the X and Y Index Registers
are set to 00. To save previous values, these bytes must always be stored before changing modes. Note
that the low byte of the S, X and Y Registers and the low and high byte of the Accumulator (A and B) are
not affected by a mode change.
7.12
How Hardware Interrupts, BRK, and COP Instructions Affect the Program Bank and the Data
Bank Registers
7.12.1
When in the Native mode, the Program Bank register (PBR) is cleared to 00 when a
hardware interrupt, BRK or COP is executed. In the Native mode, previous PBR
contents is automatically saved on Stack.
In the Emulation mode, the PBR and DBR registers are cleared to 00 when a hardware
interrupt, BRK or COP is executed. In this case, previous contents of the PBR are not
automatically saved.
Note that a Return from Interrupt (RTI) should always be executed from the same "mode"
which originally generated the interrupt.
7.12.2
7.12.3
7.13
Binary Mode
The Binary Mode is set whenever a hardware or software interrupt is executed. The D flag within the
Status Register is cleared to zero.
7.14
WAI Instruction
The WAI instruction pulls RDY low and places the processor in the WAI "low power" mode. NMIB,
IRQB or RESB will terminate the WAI condition and transfer control to the interrupt handler routine.
Note that an ABORTB input will abort the WAI instruction, but will not restart the processor. When the
Status Register I flag is set (IRQB disabled), the IRQB interrupt will cause the next instruction (following
the WAI instruction) to be executed without going to the IRQB interrupt handler. This method results in
the highest speed response to an IRQB input. When an interrupt is received after an ABORTB which
occurs during the WAI instruction, the processor will return to the WAI instruction. Other than RESB
(highest priority), ABORTB is the next highest priority, followed by NMIB or IRQB interrupts.
7.15
The STP Instruction
The STP instruction disables the PHI2 clock to all internal circuitry. When disabled, the PHI2 clock is
held in the high state. In this case, the Data Bus will remain in the data transfer state and the Bank address
will not be multiplexed onto the Data Bus. Upon executing the STP instruction, the RESB signal is the
only input which can restart the processor. The processor is restarted by enabling the PHI2 clock, which
occurs on the falling edge of the RESB input. Note that the external oscillator must be stable and operating
properly before RESB goes high.
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