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參數(shù)資料
| 型號(hào)： | W65C832PL-8 |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 24/62頁 |
| 文件大?。?/td> | 891K |
| 代理商： | W65C832PL-8 |
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WESTERN DESIGN CENTER
W65C816S
March 1, 2000
24
3.5.23
The second byte of the instruction is added to the Stack Pointer to form a pointer to the low-order 16-bit
base address in Bank 0. The Data Bank Register contains the high-order 8 bits of the base address. The
effective address is the sum of the 24-bit base address and the Y Index Register.
Stack Relative Indirect Indexed-(d,s),y
Instruction:
OpCode
offset
Stack Pointer
offset
00
S + offset
then +
DBR
base address
+
Y Reg
Operand Address:
effective address
3.5.24
This addressing mode is used by the Block Move instructions. The second byte of the instruction contains
the high-order 8 bits of the destination address. The Y Index Register contains the low-order 16 bits of the
destination address. The third byte of the instruction contains the high-order 8 bits of the source address.
The X Index Register contains the low-order bits of the source address. The C Accumulator contains one
less than the number of bytes to move. The second byte of the block move instructions is also loaded into
the Data Bank Register.
Block Source Bank, Destination Bank-xyc
Instruction:
Source Address:
Dest. Address;
OpCode
dstbnk
dstbnk
Y
DBR
srcbnk
DBR
srcbnk
X Reg
Y Reg
Increment (MVN) or decrement (MVP) X and Y.
Decrement C (if greater than zero), then PC+3
6
PC.
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