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參數(shù)資料
| 型號： | W671540P |
| 廠商： | WINBOND ELECTRONICS CORP |
| 元件分類： | 模擬傳輸電路 |
| 英文描述： | TELECOM-SLIC, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 16/42頁 |
| 文件大?。?/td> | 1230K |
| 代理商： | W671540P |
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W671500 SERIES
7.2.5. Unbalanced Ringing Mode
The W671570 and W671571 also offer an Unbalanced Ringing mode (010). This feature is important
for those Analog PBX Trunk Lines that require the Tip terminal to be held near ground for the duration
of the ringing bursts. The Tip terminal is offset to 0V using an internal current source that is applied to
the inverting input of the Tip amplifier. This reduces the differential ringing gain to 40V/V. The Ring
terminal will center at VBH/2 and swing from -VBH to ground. As in Balanced Ringing mode, off-hook
detection is accomplished by sensing the peak current and comparing it to a preset threshold. This
allows the same sensing, comparing and threshold circuitry to be used in both Ringing and
Unbalanced Ringing modes. This mode of operation does not require any additional external
components.
7.2.6. Forward Loop Back Mode
The Forward Loop Back mode (FLB, 101) provides test capability for the device. An internal signal
path is enabled allowing for both DC and AC verification. The internal 600 terminating resistor has a
tolerance of ±20%. The device is intended to operate from only the low battery during this mode.
7.2.6.1. Architecture
When the Forward Loop Back mode is initiated internal switches connect a 600 load across the
outputs of the Tip and Ring amplifiers.
RING AMP
TIP AMP
RING
TIP
600
FIGURE 11: FORWARD LOOP BACK INTERNAL TERMINATION
7.2.6.2. DC Verification
When the internal signal path is provided, DC current will flow from Tip to Ring. The DC current will
force DET LOW, indicating the presence of loop current. In addition, the ALM output will also go
LOW. In this mode this does not indicate a thermal alarm condition. Rather, proper logic operation is
verified in the event of a thermal shutdown. In addition to verifying device functionality, toggling the
logic outputs verifies the interface to the system controller.
Publication Release Date: April 2004
- 23 -
Revision 1.0
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