Publication Release Date: January 2009 - 7 - Revision A11 6. PIN DESCRIPTION Pin Name Pin No. Functionality RO+ 1 Non-inv" />
參數(shù)資料
型號(hào)： W681511DK
廠商： Nuvoton Technology Corporation of America
文件頁(yè)數(shù)： 30/32頁(yè)
文件大小： 0K
描述： KIT DEVELOPMENT FOR W681511
標(biāo)準(zhǔn)包裝： 1
主要目的： 音頻編解碼器
已用 IC / 零件： W681511
已供物品： 板，電源
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W681511
Publication Release Date: January 2009
- 7 -
Revision A11
6. PIN DESCRIPTION
Pin
Name
Pin
No.
Functionality
RO+
1
Non-inverting output of the receive smoothing filter. This pin can typically drive a 2 k
Ω load to
1.575 volt peak referenced to the analog ground level.
NC
2
Not connected.
PAI
3
This pin is the inverting input to the power amplifier. Its DC level is at the VAG voltage.
PAO-
4
Inverting power amplifier output. This pin can drive a 300
Ω load to 1.575 volt peak referenced
to the VAG voltage level.
PAO+
5
Non-inverting power amplifier output. This pin can drive a 300
Ω load to 1.575 volt peak
referenced to the VAG voltage level.
VDD
6
Power supply. This pin should be decoupled to VSS with a 0.1μF ceramic capacitor.
FSR
7
8 kHz Frame Sync input for the PCM receive section. This pin also selects channel 0 or
channel 1 in the GCI and IDL modes. It can also be connected to the FST pin when transmit
and receive are synchronous operations.
PCMR
8
PCM input data receive pin. The data needs to be synchronous with the FSR and BCLKR pins.
BCLKR
9
PCM receive bit clock input pin. This pin also selects the interface mode. The GCI mode is
selected when this pin is tied to VSS. The IDL mode is selected when this pin is tied to VDD.
This pin can also be tied to the BCLKT when transmit and receive are synchronous operations.
PUI
10
Power up input signal. When this pin is tied to VDD, the part is powered up. When tied to VSS,
the part is powered down.
MCLK
11
System master clock input. Possible input frequencies are 256 kHz, 512 kHz, 1536 kHz, 1544
kHz, 2048 kHz, 2560 kHz & 4096 kHz. For a better performance, it is recommended to have
the MCLK signal synchronous and aligned to the FST signal.
This is a requirement in the
case of 256 and 512 kHz frequency.
BCLKT
12
PCM transmit bit clock input pin.
PCMT
13
PCM output data transmit pin. The output data is synchronous with the FST and BCLKT pins.
FST
14
8 kHz transmit frame sync input. This pin synchronizes the transmit data bytes.
VSS
15
This is the supply ground. This pin should be connected to 0V.
μ/A-Law
16
Compander mode select pin.
μ-Law companding is selected when this pin is tied to V
DD. A-Law
companding is selected when this pin is tied to VSS.
AO
17
Analog output of the first gain stage in the transmit path.
AI-
18
Inverting input of the first gain stage in the transmit path.
AI+
19
Non-inverting input of the first gain stage in the transmit path.
VAG
20
Mid-Supply analog ground pin, which supplies a 2.5 Volt reference voltage for all-analog signal
processing. This pin should be decoupled to VSS with a 0.01μF to 0.1 μF capacitor. This pin
becomes high impedance when the chip is powered down.
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