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參數(shù)資料
| 型號： | W72M64VB100BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA159 |
| 封裝： | 13 X 22 MM, PLASTIC, BGA-159 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 660K |
| 代理商： | W72M64VB100BI |
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
W72M64VB-XBX
June 2009
Rev. 2
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – WE# CONTROLLED
VCC = 3.3V ± 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
Write Cycle Time (3)
tAVAV
tWC
90
100
120
ns
Chip Select Setup Time (3)
tELWL
tCS
000
ns
Lo rate Enable Pulse Width
tWLWH
tWP
35
50
ns
Address Setup Time
tAVWL
tAS
000
ns
Data Setup Time
tDVWH
tDS
45
50
ns
Data Hold Time
tWHDX
tDH
000
ns
Address Hold Time
tWLAX
tAH
45
50
ns
Lo rate Enable Pulse Width High (3)
tWHWL
tWPH
30
ns
Duration of Word Programming Operation (1)
tWHWH1
360
μs
Sector Erase (2) (5)
tWHWH2
10
sec
Read Recovery Time before Write (3)
tGHWL
000
ns
VCC Setup Time
tVCS
50
μs
Chip Programming Time (4)
42
sec
Address Setup Time to OE# low during toggle
bit polling
tASO
15
ns
Write Recovery Time from RY/BY# (3)
tRB
000
ns
Program/Erase Valid to RY/BY#
tBUSY
90
ns
NOTES:
1.
Typical value for tWHWH1 is 7μs.
2.
Typical value for tWHWH2 is 0.4 sec.
3.
Guaranteed by design, but not tested.
4.
Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip
programming time listed, since most bytes program faster than the maximum program times listed.
5.
At temperatures > + 85C maximum erase time is 25s
AC CHARACTERISTICS – READ-ONLY OPERATIONS
VCC = 3.3V ± 0.3V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
-90
-100
-120
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time (1)
tAVAV
tRC
90
100
120
ns
Address Access Time
tAVQV
tACC
90
100
120
ns
Chip Select Access Time
tELQV
tCE
90
100
120
ns
Output Enable to Output Valid
tGLQV
tOE
36
40
50
ns
Chip Select High to Output High Z
tEHQZ
tDF
16
20
ns
Output Enable High to Output High Z
tGHQZ
tDF
16
20
ns
Output Hold from Addresses, CS# or OE#
Change, Whichever occurs rst
tAXQX
tOH
0
ns
Output Enable Hold Time (1)
Read
tOEH
00
0
Toggle and
Data# Polling
10
Latency between read.write operations
tSR/W
20
1.
Guaranteed by design, not tested.
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