參數(shù)資料
型號(hào): W72M64VK120BM
英文描述: 2Mx64 3.3V Simultaneous Operation Flash Multi-Chip Package
中文描述: 2Mx64 3.3V的同時(shí)閃電行動(dòng)多芯片封裝
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 568K
代理商: W72M64VK120BM
5
White Electronic Designs Corporation (602) 437-1520 www.wedc.com
White Electronic Designs
W72M64VK-XBX
April 2005
Rev. 0
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS – WE# CONTROLLED
V
CC
= 3.3V ± 0.3V, -55°C ≤ T
A
≤ +125°C
Parameter
Symbol
-90
-100
-120
Unit
Min
90
0
35
0
45
0
45
30
Max
Min
100
0
50
0
50
0
50
30
Max
Min
120
0
50
0
50
0
50
30
Max
Write Cycle Time (3)
Chip Select Setup Time (3)
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High (3)
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write (3)
VCC Setup Time
Chip Programming Time (4)
Address Setup Time to OE# low during toggle
bit polling
Write Recovery Time from RY/BY# (3)
Program/Erase Valid to RY/BY#
NOTES:
1.
Typical value for t
WHWH
1
is 7μs.
2.
Typical value for t
WHWH
2
is 0.4 sec.
3.
Guaranteed by design, but not tested.
4.
Typical value is 36 sec. The typical chip programming time is considerably less than the maximum chip
programming time listed, since most bytes program faster than the maximum program times listed.
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
ns
ns
ns
ns
ns
ns
ns
ns
μs
sec
ns
μs
sec
ns
300
5
300
5
300
5
0
0
0
50
50
50
42
42
42
t
ASO
15
15
15
t
RB
t
BUSY
0
0
0
ns
ns
90
90
90
AC CHARACTERISTICS – READ-ONLY OPERATIONS
V
CC
= 3.3V ± 0.3V, -55°C ≤ T
A
≤ +125°C
Symbol
Min
t
AVAV
t
RC
90
t
AVQV
t
ACC
t
ELQV
t
CE
t
GLQV
t
OE
t
EHQZ
t
DF
Output Enable High to Output High Z
t
GHQZ
Output Hold from Addresses, CS# or OE#
Change, Whichever occurs first
Output Enable Hold Time (1)
Read
Toggle and
Data# Polling
Parameter
-90
-100
-120
Unit
Max
Min
100
Max
Min
120
Max
Read Cycle Time (1)
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z
ns
ns
ns
ns
ns
ns
ns
90
90
40
20
20
100
100
40
20
20
120
120
50
20
20
t
DF
t
OH
t
AXQX
0
0
0
t
OEH
0
0
10
0
10
10
1.
Guaranteed by design, not tested.
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