參數(shù)資料
型號(hào)： W78E52B-40
廠商： WINBOND ELECTRONICS CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT MTP MICROCONTROLLER
中文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PDIP40
封裝： DIP-40
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 306K
代理商： W78E52B-40
Preliminary W78E52B
- 14 -
AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the
ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the
specifications can be expressed in terms of multiple input clock periods (T
CP
), and actual parts will
usually experience less than a
±
20 nS variation. The numbers below represent the performance
expected from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
T
T
XTAL1
F
CH
CL
OP,
T
CP
PARAMETER
SYMBOL
F
OP
T
CP
T
CH
T
CL
MIN.
0
25
10
10
TYP.
-
-
-
-
MAX.
40
-
-
-
UNIT
MHz
nS
nS
nS
NOTES
1
2
3
3
Operating Speed
Clock Period
Clock High
Clock Low
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
CP
specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
T
AAS
T
AAH
T
APL
T
PDA
T
PDH
T
PDZ
T
ALW
T
PSW
MIN.
1 T
CP
-
1 T
CP
-
1 T
CP
-
-
0
0
2 T
CP
-
3 T
CP
-
TYP.
-
-
-
-
-
-
2 T
CP
3 T
CP
MAX.
-
-
-
2 T
CP
1 T
CP
1 T
CP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
4
1, 4
4
2
3
Address Valid to ALE Low
Address Hold from ALE Low
ALE Low to
PSEN
Low
PSEN
Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
PSEN Pulse Width
4
4
Notes:
1. P0.0
P0.7, P2.0
P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to PSEN going high.
4. "
" (due to buffer driving delay and wire loading) is 20 nS.
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