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參數(shù)資料
| 型號(hào)： | W78L33 |
| 文件頁(yè)數(shù)： | 6/14頁(yè) |
| 文件大小： | 131K |
| 代理商： | W78L33 |
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W78L33
- 6 -
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.
An internal trigger circuit in the reset line is used to deglitch the reset line when the W78L33 is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1,
Example: P4
REG
0D8H
MOV
P4, #0AH
; Output data "A" through P4.0
P4.3.
MOV
A, P4
; Read P4 status to Accumulator.
SETB
P4.0
; Set bit P4.0
CLR
P4.1
; Clear bit P4.1
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
V
CC
V
SS
V
IN
T
A
T
ST
MIN.
-0.3
V
SS
-0.3
0
-55
MAX.
+7.0
V
CC
+0.3
70
+150
UNIT
V
V
°
C
°
C
DC Power Supply
Input Voltage
Operating Temperature
Storage Temperature
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the
device.
DC CHARACTERISTICS
(V
DD
V
SS
= 5V
±
10%, T
A
= 25
°
C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
SPECIFICATION
MIN.
1.8
-
-
-
-
-
-
UNIT
TEST CONDITIONS
MAX.
5.5
20
3
6
1.5
50
20
Operating Voltage
Operating Current
V
DD
I
DD
V
mA
mA
mA
mA
μ
A
μ
A
No load, V
DD
= 5.5V, 20 MHz
No load, V
DD
= 2.0V, 16 MHz
V
DD
= 5.5V, Fosc = 20 MHz
V
DD
= 2.0V, Fosc = 16 MHz
V
DD
= 5.5V, Fosc = 20 MHz
V
DD
= 2.0V, Fosc = 16 MHz
Idle Current
I
IDLE
Power Down Current
I
PWDN
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